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W78E51B_05 Datasheet, PDF (17/25 Pages) Winbond – 8-BIT MICROCONTROLLER
W78E51B
8.3.4 Data Write Cycle
PARAMETER
ALE Low to WR Low
Data Valid to WR Low
Data Hold from WR High
WR Pulse Width
SYMBOL
TDAW
TDAD
TDWD
TDWR
Note: "Δ" (due to buffer driving delay and wire loading) is 20 nS.
MIN.
3 TCP -Δ
1 TCP -Δ
1 TCP -Δ
6 TCP -Δ
TYP.
-
-
-
6 TCP
MAX.
3 TCP +Δ
-
-
-
UNIT
nS
nS
nS
nS
8.3.5 Port Access Cycle
PARAMETER
Port Input Setup to ALE Low
Port Input Hold from ALE Low
Port Output to ALE
SYMBOL
TPDS
TPDH
TPDA
MIN.
1 TCP
0
1 TCP
TYP.
-
-
-
MAX.
-
-
-
UNIT
nS
nS
nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
8.3.6 Program Operation
PARAMETER
VPP Setup Time
Data Setup Time
Data Hold Time
Address Setup Time
Address Hold Time
SYMBOL
TVPS
TDS
TDH
TAS
TAH
MIN.
2.0
2.0
2.0
2.0
0
TYP.
-
-
-
-
-
MAX.
-
-
-
-
-
UNIT
μS
μS
μS
μS
μS
CE Program Pulse Width for Program
Operation
OECTRL Setup Time
OECTRL Hold Time
OE Setup Time
OE High to Output Float
Data Valid from OE
TPWP
TOCS
TOCH
TOES
TDFP
TOEV
290
300
310
μS
2.0
-
-
μS
2.0
-
-
μS
2.0
-
-
μS
0
-
130
nS
-
-
150
nS
Note: Flash data can be accessed only in flash mode. The RST pin must pull in VIH status, the ALE pin must pull in VIL status,
and the PSEN pin must pull in VIH status.
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Publication Release Date: Sep. 6, 2005
Revision A7