W9812G6KH Datasheet, PDF (14/42 Pages) Winbond – 2M X 4 BANKS X 16 BITS SDRAM

W9812G6KH
9.3 Capacitance
(VDD = 3.3V ± 0.3V, f = 1 MHz, TA = 25°C)
PARAMETER
Input Capacitance
(A0 to A11, BS0, BS1, CS , RAS , CAS , WE , DQM, CKE)
Input Capacitance (CLK)
Input/Output capacitance (DQ0DQ15)
Note: These parameters are periodically sampled and not 100% tested.
SYM.
CI
CCLK
CIO
MIN.
-
-
-
MAX.
3.8
3.5
6.5
UNIT
pf
pf
pf
9.4 DC Characteristics
(VDD = 3.3V ± 0.3V, TA = 0 to 70°C for -5/-6/-75, TA= -40 to 85°C for -6I,)
PARAMETER
SYM.
-5
MAX.
Operating Current
t_CK = min., t_RC = min.
1 Bank operation
IDD1
55
Active precharge command
cycling without burst operation
Standby Current
tCK = min., CS = VIH
VIH/L = VIH (min.)/VIL (max.)
CKE = VIH
IDD2
25
Bank: Inactive state
CKE = VIL
IDD2P
2
(Power Down Mode)
Standby Current
CLK = VIL, CS = VIH
VIH/L=VIH (min.)/VIL (max.)
CKE = VIH
IDD2S
12
Bank: Inactive state
CKE = VIL
IDD2PS
2
(Power Down Mode)
No Operating Current
t_CK = min., CS = VIH(min)
CKE = VIH
IDD3
40
Bank: Active state (4 Banks)
CKE = VIL
IDD3P
12
(Power Down Mode)
Burst Operating Current
t_CK = min.
Read/ Write command cycling
IDD4
80
Auto Refresh Current
t_CK = min.
Auto refresh command cycling
IDD5
70
Self Refresh Current
Self Refresh Mode
IDD6
2
CKE = 0.2V
-6/-6I
MAX.
50
20
2
12
2
35
12
75
65
2
-75
MAX.
45
20
2
12
2
30
12
70
60
2
UNIT NOTES
3
3
3
mA
3, 4
3
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Publication Release Date: Apr. 18, 2014
Revision: A02