W78LE51 Datasheet, PDF (14/21 Pages) Winbond – 8-BIT MTP MICROCONTROLLER

Preliminary W78LE51
Program Fetch Cycle
PARAMETER
SYMBOL MIN.
Address Valid to ALE Low
TAAS
1 TCP -∆
Address Hold from ALE Low
TAAH
1 TCP -∆
ALE Low to PSEN Low
TAPL
1 TCP -∆
PSEN Low to Data Valid
TPDA
-
Data Hold after PSEN High
TPDH
0
Data Float after PSEN High
TPDZ
0
ALE Pulse Width
TALW
2 TCP -∆
PSEN Pulse Width
TPSW
3 TCP -∆
Notes:
1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 TCP.
3. Data have been latched internally prior to PSEN going high.
4. "∆" (due to buffer driving delay and wire loading) is 20 nS.
TYP.
-
-
-
-
-
-
2 TCP
3 TCP
MAX.
-
-
-
2 TCP
1 TCP
1 TCP
-
-
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
NOTES
4
1, 4
4
2
3
4
4
Data Read Cycle
PARAMETER
ALE Low to RD Low
RD Low to Data Valid
Data Hold from RD High
Data Float from RD High
RD Pulse Width
SYMBOL
TDAR
TDDA
TDDH
TDDZ
TDRD
MIN.
3 TCP -∆
-
0
0
6 TCP -∆
Notes:
1. Data memory access time is 8 TCP.
2. "∆" (due to buffer driving delay and wire loading) is 20 nS.
TYP.
-
-
-
-
6 TCP
MAX.
3 TCP +∆
4 TCP
2 TCP
2 TCP
-
UNIT
nS
nS
nS
nS
nS
NOTES
1, 2
1
2
Data Write Cycle
PARAMETER
ALE Low to WR Low
Data Valid to WR Low
Data Hold from WR High
WR Pulse Width
SYMBOL
TDAW
TDAD
TDWD
TDWR
MIN.
3 TCP -∆
1 TCP -∆
1 TCP -∆
6 TCP -∆
Note: "∆" (due to buffer driving delay and wire loading) is 20 nS.
TYP.
-
-
-
6 TCP
MAX.
3 TCP +∆
-
-
-
UNIT
nS
nS
nS
nS
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