W681513_05 Datasheet, PDF (12/35 Pages) Winbond – 5V SINGLE-CHANNEL VOICEBAND CODEC FOR USB APPLICATIONS

W681513
7.4.4. Interchip Digital Link (IDL)
The IDL interface mode is selected when the BCLKR pin is connected to V_DD for two or more frame
sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The IDL interface
consists of 4 pins: IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (PCMT) & IDL RX (PCMR). The FSR
pin selects channel B1 or B2 for transmit and receive. The data for channel B1 is transmitted on the
first positive edge of the IDL CLK after the IDL SYNC pulse. The IDL SYNC pulse is one IDL CLK
cycle long. The data for channel B2 is transmitted on the eleventh positive edge of the IDL CLK after
the IDL SYNC pulse. The data for channel B1 is received on the first negative edge of the IDL CLK
after the IDL SYNC pulse. The data for channel B2 is received on the eleventh negative edge of the
IDL CLK after the IDL SYNC pulse. The transmit signal pin IDL TX becomes high impedance when
not used for data transmission and also in the time slot of the unused channel. For more timing
information, see the timing section.
7.4.5. System Timing
The system can work at 2000 kHz master clock rate only. The system clock is supplied through the
master clock input MCLK and can be derived from the bit-clock if desired. An internal pre-scaler is
used to generate a fixed 256 kHz and 8 kHz sample clock for the internal CODEC. If the Frame Sync
is LOW for the entire frame sync period while the MCLK and BCLK pin clock signals are still present,
the W681513 will enter the low power standby mode. Another way to power down is to set the PUI pin
to low. When the system needs to be powered up again, the PUI pin needs to be set to HIGH and the
Frame Sync pulse needs to be present. It will take two Frame Sync cycles before the pin PCMT will
become low impedance.
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