W29C512A Datasheet, PDF (11/20 Pages) Winbond – 64 K x 8 CMOS FLASH MEMORY

W29C512A
Read Cycle Timing Parameters
(VDD = 5.0V ± 5%, VSS = 0V, TA = 0 to 70° C)
PARAMETER
Read Cycle Time
Chip Enable Access Time
Address Access Time
Output Enable Access Time
#CE High to Hight-Z Output
#WE High to High-Z Output
Output Hold from Address Change
SYM.
TRC
TCE
TAA
TOE
TCHZ
TOHZ
TOH
W29C512A-90
MIN.
MAX.
90
-
-
90
-
90
-
40
-
25
-
25
0
-
UNIT
nS
nS
nS
nS
nS
nS
nS
Byte/Page-write Cycle Timing Parameters
PARAMETER
Write Cycle (Erase and Program)
Address Setup Time
Address Hold Time
#WE and #CE Setup Time
#WE and #CE Hold Time
#OE High Setup Time
#OE High Hold Time
#CE Pulse Width
#WE Pulse Width
#WE High Width
Data Setup Time
Data Hold Time
Byte Load Cycle Time
SYMBOL
TWC
TAS
TAH
TCS
TCH
TOES
TOEH
TCP
TWP
TWPH
TDS
TDH
TBLC
MIN.
-
0
50
0
0
0
0
90
90
100
35
0
-
TYP.
-
-
-
-
-
-
-
-
-
-
-
-
-
MAX.
10
-
-
-
-
-
-
-
-
-
-
-
150
Notes: All AC timing signals observe the following guidelines for determining setup and hold times:
(1) High level signal's reference level is VIH.
(2) Low level signal's reference level is VIL.
UNIT
mS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
µS
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Publication Release Date: February 5, 2002
Revision A2