W523A008 Datasheet, PDF (10/19 Pages) Winbond – HIGH FIDELITY POWER SPEECH

W523AXXX
5.4 CPU Interface
The W523Axxx can communicate with an external microprocessor through a simple serial CPU
interface. The CPU interface consists of TG1, TG2 and STPA/BUSY pins, which are shown below:
TG1
(Data)
TG2
(Clock)
TDEB
STPA/Busy
Debounced OK. to clear the internal CPU
counter for preventing the system from
running away. (TG1F should be disabled.)
TCRD
END
AUD/SPK+
Notes:
1. TDEB means the "Debounce time".
2. TCRD is the "CPU Reset Delay" time. This should be more than 2.6 µS.
3. The "Clock" frequency of the TG2 pin can be set in the range: 10 KHz - 1 MHz.
Busy signal will output "high" after the end of transmission. The rising timing of Busy signal is
dependent on the MSB of data output on TG1 (Data) pin. If MSB is "1", Busy will rise after the last
rising edge of TG2 (Clock) pin. If MSB is "0", Busy will rise after the rising edge that TG1 (Data)
returns to high.
TG1
(DATA)
TG2
(CLK)
BUSY
7 bits
MSB=0
40ns
TG1
(DATA)
TG2
(CLK)
BUSY
7 bits
MSB=1
40ns
- 10 -