CG6264AM Datasheet, PDF (8/12 Pages) Weida Semiconductor, Inc. – 2Mb (128K x 16) Pseudo Static RAM

ADVANCE INFORMATION
Switching Waveforms (continued)
Write Cycle 1 (WE Controlled) ^{[13, 14,17, 18, 19]}
ADDRESS
CE
t_WC
t_SCE
CE2
t_AW
t_SA
t_PWE
WE
BHE/BLE
t_BW
CG6264AM
t_HA
OE
DATA I/O _{DON’T CARE}
Write Cycle 2 (CE or CE₂ Controlled)^{[13, 14,17, 18, 19]}
ADDRESS
CE
t_SD
VALID DATA
t_WC
t_SCE
CE2
WE
t_SA
t_AW
t_PWE
BHE/BLE
t_BW
t_HD
t_HA
OE
DATA I/O
DON’T CARE
t_SD
t_HD
VALID DATA
t_HZOE
Notes:
17. Data I/O is high impedance if OE = V_IH.
18. If Chip Enable goes INACTIVE and CE₂ goes LOW simultaneously with WE = V_IH, the output remains in a high-impedance state.
19. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
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