CG6264AM Datasheet, PDF (7/12 Pages) Weida Semiconductor, Inc. – 2Mb (128K x 16) Pseudo Static RAM

ADVANCE INFORMATION
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)^{[15, 16]}
t_RC
ADDRESS
DATA OUT
t_SK
t_OHA
t_AA
PREVIOUS DATA VALID
CG6264AM
DATA VALID
Read Cycle 2 (OE Controlled)^{[15, 16]}
ADDRESS
CE
t_SK
t_RC
CE2
BHE/BLE
t_ACE
t_LZBE
t_DBE
OE
DATA OUT
VCC
t_DOE
t_LZOE
HIGH IMPEDANCE
t_LZCE
t_PU
Note:
15. WE is HIGH for read cycle.
16. Addresses should not be toggled after the start of a read cycle
t_PD
t_HZCE
t_HZBE
t_HZOE
DATA VALID
HIGH
IMPEDANCE
I_CC
50%
38-XXXXX
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