WCMS0808U1X Datasheet, PDF (4/10 Pages) Weida Semiconductor, Inc. – 32K x 8 Static RAM

WCMS0808U1X
Switching Characteristics Over the Operating Range^[5]
WCMS0808U1X
Parameter
Description
Min.
Max.
Unit
READ CYCLE
t_RC
Read Cycle Time
t_AA
Address to Data Valid
t_OHA
Data Hold from Address Change
t_ACE
CE LOW to Data Valid
t_DOE
t_LZOE
t_HZOE
t_LZCE
t_HZCE
OE LOW to Data Valid
OE LOW to Low Z^[6]
OE HIGH to High Z^{[6, 7]}
CE LOW to Low Z^[6]
CE HIGH to High Z^{[6, 7]}
t_PU
CE LOW to Power-Up
t_PD
CE HIGH to Power-Down
WRITE CYCLE^[8,9]
70
ns
70
ns
10
ns
70
ns
35
ns
5
ns
25
ns
10
ns
25
ns
0
ns
70
ns
t_WC
Write Cycle Time
70
ns
t_SCE
CE LOW to Write End
60
ns
t_AW
Address Set-Up to Write End
60
ns
t_HA
Address Hold from Write End
0
ns
t_SA
Address Set-Up to Write Start
0
ns
t_PWE
WE Pulse Width
50
ns
t_SD
Data Set-Up to Write End
30
ns
t_HD
t_HZWE
t_LZWE
Data Hold from Write End
WE LOW to High Z^{[6, 7]}
WE HIGH to Low Z^[6]
0
ns
25
ns
10
ns
Notes:
4. No input may exceed V_CC+0.3V.
5. Test conditions assume signal transition time of 5 ns or less timing reference levels of Vcc/2, input pulse levels of 0 to Vcc, and output
loading of the specified I_OL/I_OH and 100-pF load capacitance.
6. At any given temperature and voltage condition, t_HZCE is less than t_LZCE, t_HZOE is less than t_LZOE, and t_HZWE is less than t_LZWE for any given
device.
7. t_HZOE, t_HZCE, and t_HZWE are specified with C_L = 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that
terminates the write.
9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t_HZWE and t_SD
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