WCFS4016V1C Datasheet, PDF (4/9 Pages) Weida Semiconductor, Inc. – 256K x 16 Static RAM

WCFS4016V1C
AC Switching Characteristics^[3] Over the Operating Range
Parameter
READ CYCLE
t_power[4]
t_RC
t_AA
t_OHA
t_ACE
t_DOE
t_LZOE
t_HZOE
t_LZCE
t_HZCE
t_PU
t_PD
t_DBE
t_LZBE
t_HZBE
WRITE CYCLE^{[7, 8]}
t_WC
t_SCE
t_AW
t_HA
t_SA
t_PWE
t_SD
t_HD
t_LZWE
t_HZWE
t_BW
Description
V_CC(typical) to the first access
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z^{[5, 6]}
CE LOW to Low Z^[6]
CE HIGH to High Z^{[5, 6]}
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z^[6]
WE LOW to High Z^{[5, 6]}
Byte Enable to End of Write
WCFS4016V1C 12ns
Min.
Max.
Unit
1
µs
12
ns
12
ns
3
ns
12
ns
6
ns
0
ns
6
ns
3
ns
6
ns
0
ns
12
ns
6
ns
0
ns
6
ns
12
ns
8
ns
8
ns
0
ns
0
ns
8
ns
6
ns
0
ns
3
ns
6
ns
8
ns
Notes:
3. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
4. t_POWER gives the minimum amount of time that the power supply should be at typical Vcc values until the first memory access can be performed.
5. t_HZOE, t_HZCE, and t_HZWE are specified with a load capacitance of 5pF as in part (a) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
6. At any given temperature and voltage condition, t_HZCE is less than t_LZCE, t_HZOE is less than t_LZOE, and t_HZWE is less than t_LZWE for any given device.
7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t_HZWE and t_SD.
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