WC32P020-XXM Datasheet, PDF (8/14 Pages) White Electronic Designs Corporation – 16 32-Bit General-Purpose Data and Address Registers

White Electronic Designs
WC32P020-XXM
AC ELECTRICAL SPECIFICATIONS – READ AND WRITE CYCLES
VCC = 5.0 VDC ± 5%, GND = 0 VDC, -55°C ≤ TA ≤ +125°C
16.67 MHz
20 MHz
25 MHz
Characteristic
Specification Min Max Min Max Min Max Unit
Clock high to Address, FC, Size, RMC# Valid
6
0
30
0
25
0
25
ns
Clock High to ECS#, OCS# Asserted
6A
0
20
0
15
0
12
ns
Clock High to Address, Data, FC, Size, RMC#, High Impedance
7
0
60
0
50
0
40
ns
Clock high to Address, FC, Size, RMC# Invalid
8
0
—
0
—
0
—
ns
Clock Low to AS#, DS# Asserted
9
1
30
1
25
1
18
ns
AS# to DS# Assertion (Read) (Skew)
9A (1)
-15
15
-10
10
-10
10
ns
AS# Asserted to DS# Asserted (Write)
9B (11)
37
—
32
—
27
—
ns
ECS# Width Asserted
10
20
—
15
—
15
—
ns
OCS# Width Asserted
10
20
—
15
—
15
—
ns
ECS#, OCS# width Negated
10B (7)
15
—
10
—
5
—
ns
Address, FC, Size, RMC#, Valid to AS# (and DS# Asserted Read)
11
15
—
10
—
6
—
ns
Clock Low to AS#, DS# Negated
12
0
30
0
25
0
15
ns
Clock Low to ECS#, OCS# Negated
12A
0
30
0
25
0
15
ns
AS#, DS# Negated to Address, FC, Size, RMC# Invalid
13
15
—
10
—
10
—
ns
AS# (and DS# Read) Width Asserted
14
100
—
85
—
70
—
ns
DS# Width Asserted Write
14A
40
—
38
—
30
—
ns
AS#, DS# Width Negated
15
40
—
38
—
30
—
ns
DS# Negated to AS# Asserted
15A (8)
35
—
30
—
25
—
ns
Clock High to AS#, DS#, R/W# Invalid, High Impedance
16
—
60
—
50
—
40
ns
AS#, DS# Negated to R/W# Invalid
17
15
—
10
—
10
—
ns
Clock High to R/W# High
18
0
30
0
25
0
20
ns
Clock High to R/W# Low
20
0
30
0
25
0
20
ns
R/W# High to AS# Asserted
21
15
—
10
—
5
—
ns
R/W# Low to DS# Asserted (Write)
22
75
—
60
—
50
—
ns
Clock High to Data Out Valid
23
—
30
—
25
—
25
ns
DS# Negated to Data Out Invalid
25
15
—
10
—
5
—
ns
DS# Negated to DBEN# Negated (Write)
25A (9)
15
—
10
—
5
—
ns
Data Out Valid to DS# Asserted (Write)
26
15
—
10
—
5
—
ns
Data-In Valid to Clock Low (Data Setup)
27
5
—
5
—
5
—
ns
Late BERR#/HALT# Asserted to Clock Low Setup Time
27A
20
—
15
—
10
—
ns
AS#, DS# Negated to DSACKx#, BERR#, HALT#, AVEC# Negated
28
0
80
0
65
0
50
ns
DS# Negated to Data-In Invalid (Data-In Hold Time)
29
0
—
0
—
0
—
ns
DS# Negated to Data-In (High Impedance)
29A
—
60
—
50
—
40
ns
DSACKx# Asserted to Data-In Valid
31 (2)
—
50
—
43
—
32
ns
DSACKx# Asserted to DSACKx# Valid (DSACK# Asserted Skew)
31A (3)
—
15
—
10
—
10
ns
RESET# Input Transition Time
32
—
1.5
—
1.5
—
1.5
Clks
Clock Low to BG# Asserted
33
0
30
0
25
0
20
ns
Clock Low to BG# Negated
34
0
30
0
25
0
20
ns
BR# Asserted to BG# Asserted (RMC# Not Asserted)
35
1.5
3.5
1.5
3.5
1.5
3.5
Clks
BGACK# Asserted to BG# Negated
37
1.5
3.5
1.5
3.5
1.5
3.5
Clks
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
December 2002
Rev. 2
8
White Electronic Designs Corporation • [phone] • www.wedc.com