WC32P020-XXM Datasheet, PDF (5/14 Pages) White Electronic Designs Corporation – 16 32-Bit General-Purpose Data and Address Registers

White Electronic Designs
WC32P020-XXM
Signal Name
Function Codes
Address Bus
Data Bus
Size
External Cycle Start
Operand Cycle Start
Read,Write
Read-Modify-Write Cycle
Address Strobe
Data Strobe
Data Buffer Enable
Data Transfer and Size
Acknowledge
Interrupt Priority Level
Interrupt Pending
Autovector
Bus Request
Bus Grant
Bus Grant Acknowledge
Reset
Halt
Bus Error
Cache Disable
Clock
Power Supply
Ground
Mnemonic
FC2-FC0
A0-A31
D0-D31
SIZ0/SIZ1
ECS#
OCS#
R/W#
RMC#
AS#
DS#
DBEN#
DSACK0#/DSACK1#
IPL0#-IPL2#
IPEND#
AVEC#
BR#
BG#
BGACK#
RESET#
HALT#
BERR#
CDIS#
CLK
Vcc
GND
SIGNAL INDEX
Function
3-bit function code used to identify the address space of each bus cycle.
32-bit address bus.
32-bit data bus used to transfer 8, 16, 24, or 32 bits of data per bus cycle.
Indicates the number of bytes remaining to be transferred for this cycle. These signals, together
with A1 and A0, define the active sections of the data bus.
Provides an indication that a bus cycle is beginning.
Identical operation to that of ECS except that OCS is asserted only during the first bus cycle of an
operand transfer.
Defines the bus transfer as a processor read or write.
Provides an indicator that the current bus cycle is part of an indivisible read-modify-write operation.
Indicates that a valid address is on the bus.
Indicates that valid data is to be placed on the data bus by an external device or has been placed
on the data bus by the WC32P020-XXM.
Provides an enable signal for external data buffers.
Bus response signals that indicate the requested data transfer operation has completed. In
addition, these two lines indicate the size of the external bus port on a cycle-by-cycle basis and are
used for asynchronous transfers.
Provides an encoded interrupt level to the processor.
Indicates that an interrupt is pending.
Requests an autovector during an interrupt acknowledge cycle.
Indicates that an external device requires bus mastership.
Indicates that an external device may assume bus mastership.
Indicates that an external device has assumed bus mastership.
System reset.
Indicates that the processor should suspend bus activity.
Indicates that an erroneous bus operation is being attempted.
Dynamically disables the on-chip cache to assist emulator support
Clock input to the processor.
Power supply.
Ground connection.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
December 2002
Rev. 2
5
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