W3HG128M64EEU-D4 Datasheet, PDF (8/14 Pages) White Electronic Designs Corporation – 1GB - 128Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM

White Electronic Designs
W3HG128M64EEU-D4
ADVANCED
AC OPERATING CONDITIONS (continued)
VCC = +1.8V ±0.1V
AC Characteristics
Parameter
806
665
534
Symbol
Min Max Min Max Min Max
DQS–DQ skew, DQS to last DQ valid, per group, per
access
t_DQSQ
240
240
300
403
Min Max
350
Units
ps
DQS read preamble
t_{RPRE 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1} t_CK
DQS read postamble
DQS write preamble setup time
DQS write preamble
DQS write postamble
Positive DQS latching edge to associated clock edge
Write command to first DQS latching transition
Address and control input pulse width for each input
Address and control input setup time
Address and control input hold time
Address and control input setup time
Address and control input hold time
CAS# to CAS# command delay
ACTIVE to ACTIVE (same bank) command
ACTIVE bank a to ACTIVE bank b command
ACTIVE to READ or WRITE delay
Four Bank Activate period
ACTIVE to PRECHARGE command
t_{RPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6} t_CK
t_{WPRES 0}
0
0
0
ps
t_{WPRE 0.35}
0.35
0.25
0.25
t_CK
t_{WPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6} t_CK
t_{DQSS - 0.25 0.25 - 0.25 0.25 - 0.25 0.25 - 0.25 0.25} t_CK
WL- WL+ WL- WL+ WL- WL+ WL- WL+
t_DQSS t_DQSS t_DQSS t_DQSS t_DQSS t_DQSS t_DQSS t_DQSS
t_CK
t_{IPW 0.6}
0.6
0.6
0.6
t_CK
t_ISa
400
400
500
600
ps
t_IHa
400
400
500
600
ps
t_ISb
200
200
250
350
ps
t_IHb
275
275
375
475
t_CCD
2
2
2
2
t_CK
t_RC
54
55
55
55
ns
t_RRD
7.5
7.5
7.5
7.5
ns
(x8)
t_{RCD 12}
15
15
15
ns
t_{FAW 37.5}
37.5
37.5
37.5
ns
(x8)
t_{RAS 40 70,000 40 70,000 40 70,000 40 70,000 ns}
Internal READ to precharge command delay
t_{RTP 7.5}
7.5
7.5
7.5
ns
Write recovery time
t_WR
15
15
15
15
ns
Auto precharge write recovery + precharge time
t_DAL t_{WR +} t_RP
t_{WR +} t_RP
t_{WR +} t_RP
t_{WR +} t_RP
ns
Internal WRITE to READ command delay
t_{WTR 7.5}
7.5
7.5
10
ns
PRECHARGE command period
t_RP
12
15
15
15
ns
PRECHARGE ALL command period
t_RPA t_{RP +} t_CK
t_{RP +} t_CK
t_{RP +} t_CK
t_{RP +} t_CK
ns
LOAD MODE command cycle time
t_MRD
2
2
2
2
t_CK
Note:
• AC specification is based on MICRON components. Other DRAM manufactures specification may be different.
Notes
15, 17
33, 37,
43
33, 34,
37, 43
12, 13,
37
11, 37
37
37
6, 19
6, 19
6, 19
6, 19
37
31, 37
25, 37
37
28, 37
18, 31,
37
21, 25.
37
25, 37
20
25, 37
29, 37
29
37
March 2006
Rev. 0
8
White Electronic Designs Corporation • [phone] • www.wedc.com