W3HG128M64EEU-D4 Datasheet, PDF (6/14 Pages) White Electronic Designs Corporation – 1GB - 128Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM

White Electronic Designs
W3HG128M64EEU-D4
ADVANCED
AC Characteristics
Parameter
Clock cycle time
CK high-level width
CK low-level width
Half clock period
Absolute tCk
AC OPERATING CONDITIONS
VCC = +1.8V ±0.1V
CL = 6
CL = 5
CL = 4
CL = 3
806
665
534
403
Symbol
Units
Min Max Min Max Min Max Min Max
t_{CK (6) 3,000 8,000 -}
-
-
-
-
-
ps
t_{CK (5) 3,000 8,000 3,000 8,000 -}
-
-
-
ps
t_{CK (4) 3,000 8,000 3,750 8,000 3,750 8,000 5,000 8,000 ps}
t_{CK (3) -}
- 5,000 8,000 5,000 8,000 5,000 8,000 ps
t_{CHAVG 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52} t_CK
t_{CLAVG 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52} t_CK
t_HP
MIN
(tCH,tCL)
MIN
(tCH,tCL)
MIN
(tCH,tCL)
MIN
(tCH,tCL)
ps
t_CKAVG+ t_CKAVG+ t_CKAVG+ t_CKAVG+ t_CKAVG+ t_CKAVG+ t_CKAVG+ t_CKAVG+
(MIN)+ (MAX)+ (MIN)+ (MAX)+ (MIN)+ (MAX)+ (MIN)+ (MAX)+
t_CKabs t_JITPER t_JITPER t_JITPER t_JITPER t_JITPER t_JITPER t_JITPER t_{JITPER ps}
(MIN) (MAX) (MIN) (MAX) (MIN) (MAX) (MIN) (MAX)
Notes
16, 22,
36, 38
45
46
Absolute CK high-level width
t_CKAVG t_CKAVG t_CKAVG t_CKAVG t_CKAVG t_CKAVG t_CKAVG t_CKAVG
t_CHabs
(MIN)*^tCH (MAX)*^tCH (MIN)*^tCH (MAX)*^tCH (MIN)*^tCH (MAX)*^tCH (MIN)*^tCH (MAX)*^tCH
AVG+^tJIT AVG+^tJIT AVG+^tJIT AVG+^tJIT AVG+^tJIT AVG+^tJIT AVG+^tJIT AVG+^tJIT
ps
DTY(MIN) DTY(MAX) DTY(MIN) DTY(MAX) DTY(MIN) DTY(MAX) DTY(MIN) DTY(MAX)
Absolute CK low-level width
t_CKAVG ^tCKAVG t_CKAVG ^tCKAVG t_CKAVG ^tCKAVG t_CKAVG ^tCKAVG
(MAX)*
(MAX)*
(MAX)*
(MAX)*
t_CLabs
(MIN)*
t_CLAVG
t_CLAVG
(MIN)*
t_CLAVG
t_CLAVG
(MIN)*
t_CLAVG
t_CLAVG
(MIN)*
t_CLAVG
t_CLAVG
ps
(MIN)+^tJIT
(MAX)+
t_JIT
(MIN)+^tJIT
(MAX)+
t_JIT
(MIN)+^tJIT
(MAX)+
t_JIT
(MIN)+^tJIT
(MAX)+
t_JIT
DTY(MIN)
DTY(MIN)
DTY(MIN)
DTY(MIN)
DTY(MIN)
DTY(MIN)
DTY(MIN)
DTY(MIN)
Clock jitter - period
t_{JITPER -125 125 -125 125 -125 125 -125 125 ps}
Clock jitter - half period
t_{JITDUTY -125 125 -125 125 -125 125 -150 150 ps}
Clock jitter - cycle to cycle
t_JITCC
250
250
250
250
ps
Cumulative jitter error, 2 cycles
t_{ERR2per -175 175 -175 175 -175 175 -175 175 ps}
Cumulative jitter error, 3 cycles
t_{ERR3per -225 225 -225 225 -225 225 -225 225 ps}
Cumulative jitter error, 4 cycles
t_{ERR4per -250 250 -250 250 -250 250 -250 250 ps}
Cumulative jitter error, 5cycles
t_{ERR5per -250 250 -250 250 -250 250 -250 250 ps}
Cumulative jitter error, 6-10 cycles
t_{ERR6-10per -350 350 -350 350 -350 350 -350 350 ps}
Cumulative jitter error, 11-50 cycles
t_{ERR11-50per -450 450 -450 450 -450 450 -450 450 ps}
Note:
• AC specification is based on MICRON components. Other DRAM manufactures specification may be different.
39
40
41
42
42
42
42, 48
42, 48
42
March 2006
Rev. 0
6
White Electronic Designs Corporation • [phone] • www.wedc.com