W3EG6466S-AD4 Datasheet, PDF (8/13 Pages) White Electronic Designs Corporation – 512MB - 2x32Mx64 DDR SDRAM UNBUFFERED, w/PLL

White Electronic Designs
W3EG6466S-AD4
-BD4
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC
OPERATING CONDITIONS (Continued)
AC CHARACTERISTICS
335
262
265/202
UNITS NOTES
PARAMETER
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time
DQS write postamble
Write recovery time
Internal WRITE to READ command delay
Data valid output window
REFRESH to REFRESH command interval
Average periodic refresh interval
Terminating voltage delay to VDD
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
SYMBOL MIN MAX MIN MAX MIN MAX
tQH tHP - tQHS
tHP - tQHS
tHP - tQHS
ns
tQHS
0.75
0.75
0.75 ns
tRAS
42 70,000 40 120,000 40 120,000 ns
tRAP
15
15
20
ns
tRC
60
60
65
ns
tRFC
72
75
75
ns
tRCD
15
15
20
ns
tRP
15
15
20
ns
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
tRRD
12
15
15
ns
tWPRE 0.25
0.25
0.25
tCK
tWPRES
0
0
0
ns
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
tWR
15
15
15
ns
tWTR
1
1
1
tCK
NA
tQH -tDQSQ
tQH -tDQSQ
tQH -tDQSQ
ns
tREFC
70.3
70.3
70.3 µs
tREFI
7.8
7.8
7.8
µs
tVTD
0
0
0
ns
tXSNR
75
75
75
ns
tXSRD
200
200
200
tCK
22, 23
31, 47
42
37
37
18, 19
17
22
21
21
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 2
8
White Electronic Designs Corporation • [phone] • www.wedc.com