W3EG6466S-AD4 Datasheet, PDF (5/13 Pages) White Electronic Designs Corporation – 512MB - 2x32Mx64 DDR SDRAM UNBUFFERED, w/PLL

White Electronic Designs
W3EG6466S-AD4
-BD4
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ±0.2V, VCC = 2.5V ±0.2V
DDR333@CL=2.5 DDR266@CL=2, 2.5 DDR200@CL=2
Parameter
Symbol Conditions
Max
Max
Max
Units
One device bank; Active - Precharge;
1600
1440
1360
mA
tRC=tRC(MIN); tCK=tCK(MIN); DQ,DM and DQS
Operating Current
IDD0 inputs changing once per clock cycle; Address
and control inputs changing once every two
cycles.
One device bank; Active-Read-Precharge;
1800
1640
1560
mA
Operating Current
IDD1
Burst = 2; tRC=tRC(MIN);tCK=tCK(MIN); Iout =
0mA; Address and control inputs changing
once per clock cycle.
Precharge Power-Down
Standby Current
IDD2P
All device banks idle; Power- down mode;
tCK=tCK(MIN); CKE=(low)
48
48
48
mA
CS# = High; All device banks idle;
400
320
320
mA
Idle Standby Current
IDD2F
tCK=tCK(MIN); CKE = high; Address and other
control inputs changing once per clock cycle.
Vin = Vref for DQ, DQS and DM.
Active Power-Down
Standby Current
IDD3P
One device bank active; Power-down mode;
tCK(MIN); CKE=(low)
560
480
480
mA
CS# = High; CKE = High; One device
880
720
720
mA
bank; Active-Precharge; tRC=tRAS(MAX);
Active Standby Current
IDD3N
tCK=tCK(MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address and
other control inputs changing once per clock
cycle.
Burst = 2; Reads; Continous burst; One
2160
1840
1840
mA
Operating Current
IDD4R
device bank active;Address and control inputs
changing once per clock cycle; tCK=tCK(MIN);
Iout = 0mA.
Burst = 2; Writes; Continous burst; One
2160
1800
1800
mA
device bank active; Address and control inputs
Operating Current
IDD4W changing once per clock cycle; tCK=tCK(MIN);
DQ,DM and DQS inputs changing twice per
clock cycle.
Auto Refresh Current
IDD5 tRC=tRC(MIN)
2240
2000
2000
mA
Self Refresh Current
IDD6 CKE ≤ 0.2V
48
48
48
mA
Four bank interleaving Reads (BL=4) with auto
3120
2960
2720
mA
Operating Current
IDD7A
precharge with tRC=tRC (MIN); tCK=tCK(MIN);
Address and control inputs change only
during Active Read or Write commands.
* For DDR333 consult factory
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 2
5
White Electronic Designs Corporation • [phone] • www.wedc.com