W3EG7232S-AD4 Datasheet, PDF (7/14 Pages) White Electronic Designs Corporation – 256MB - 32Mx72 DDR SDRAM UNBUFFERED w/PLL

White Electronic Designs
W3EG7232S-AD4
-BD4
PRELIMINARY
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
AC CHARACTERISTICS
335
PARAMETER
SYMBOL MIN MAX
Access window of DQs from CK/CK#
tAC -0.7 +0.7
CK high-level width
tCH 0.45 0.55
CK low-level width
tCL 0.45 0.55
Clock cycle time
CL = 2.5 tCK (2.5) 6
13
CL = 2 tCK (2) 7.5
13
DQ and DM input hold time relative to DQS
tDH 0.45
DQ and DM input setup time relative to DQS
tDS 0.45
DQ and DM input pulse width (for each input)
tDIPW 1.75
Access window of DQS from CK/CK#
tDQSCK -0.6 +0.6
DQS input high pulse width
tDQSH 0.35
DQS input low pulse width
tDQSL 0.35
DQS-DQ skew, DQS to last DQ valid, per group, per tDQSQ
0.45
access
Write command to first DQS latching transition
tDQSS 0.75 1.25
DQS falling edge to CK rising - setup time
tDSS
0.2
DQS falling edge from CK rising - hold time
tDSH
0.2
Half clock period
tHP
Data-out high-impedance window from CK/CK#
tHZ
+0.7
Data-out low-impedance window from CK/CK#
tLZ
-0.7
Address and control input hold time (slow slew rate)
tIHS 0.80
Address and control input setup time (slow slew rate) tISS 0.80
Address and Control input pulse width (for each input) tIPW 2.2
LOAD MODE REGISTER command cycle time
tMRD
12
262
MIN MAX
-0.75 +0.75
0.45 0.55
0.45 0.55
7.5 13
7.5 13
0.5
0.5
1.75
-0.75 +0.75
0.35
0.35
0.5
0.75 1.25
0.2
0.2
tCH, tCL
+0.75
-0.75
0.90
0.90
2.2
15
265
MIN MAX
-0.75 +0.75
0.45 0.55
0.45 0.55
7.5 13
7.5 13
0.5
0.5
1.75
-0.75 +0.75
0.35
0.35
0.5
0.75 1.25
0.2
0.2
+0.75
-0.75
1
1
2.2
15
202
MIN MAX UNITS NOTES
-0.75 +0.75 ns
0.45 0.55 tCK 26
0.45 0.55 tCK 26
7.5 13 ns 39, 44
10 13 ns 39, 44
0.5
ns 23, 27
0.5
ns 23, 27
1.75
ns 27
-0.75 +0.75 ns
0.35
tCK
0.35
tCK
0.6 ns 22, 23
0.75 1.25 tCK
0.2
tCK
0.2
tCK
tCH, tCL
ns 30
+0.75 ns 16, 36
-0.75
ns 16, 36
1.1
ns 12
1.1
ns 12
2.2
ns
15
ns
August 2005
Rev. 4
7
White Electronic Designs Corporation • [phone] • www.wedc.com