W3EG7232S-AD4 Datasheet, PDF (5/14 Pages) White Electronic Designs Corporation – 256MB - 32Mx72 DDR SDRAM UNBUFFERED w/PLL

White Electronic Designs
W3EG7232S-AD4
-BD4
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
DDR333@ DDR266@
CL=2.5 CL=2, 2.5
Parameter
Symbol Conditions
Max
Max
Operating Current
IDD0 One device bank; Active - Precharge; (MIN); DQ,DM and
1400
1400
DQS inputs changing once per clock cycle; Address and
control inputs changing once every two cycles. TRC=TRC(MIN);
TCK=TCK
Operating Current
IDD1 One device bank; Active-Read-Precharge; Burst = 2;
TRC=TRC(MIN);TCK=TCK (MIN); Iout = 0mA; Address and
control inputs changing once per clock cycle.
1805
1805
Precharge Power-Down IDD2P All device banks idle; Power-down mode; TCK=TCK(MIN);
Standby Current
CKE=(low)
36
36
Idle Standby Current
IDD2F CS# = High; All device banks idle; TCK=TCK(MIN); CKE = high;
725
725
Address and other control inputs changing once per clock
cycle. VIN = VREF for DQ, DQS and DM.
Active Power-Down
Standby Current
IDD3P One device bank active; Power-down mode; TCK(MIN);
CKE=(low)
270
270
Active Standby Current IDD3N CS# = High; CKE = High; One device bank; Active-Precharge;
815
815
TRC=TRAS(MAX); TCK=TCK(MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address and other control
inputs changing once per clock cycle.
Operating Current
IDD4R Burst = 2; Reads; Continous burst; One device bank
1850
1850
active;Address andcontrol inputs changing once per clock
cycle; TCK=TCK(MIN); IOUT = 0mA.
Operating Current
IDD4W Burst = 2; Writes; Continous burst; One device bank active;
1850
1850
Address and control inputs changing once per clock cycle;
TCK=TCK(MIN); DQ,DM and DQS inputs changing twice per
clock cycle.
Auto Refresh Current
IDD5 TRC=TRC(MIN)
2570
2570
Self Refresh Current
IDD6 CKE ≤ 0.2V
311
311
Operating Current
IDD7A Four bank interleaving Reads (BL=4) with auto precharge with 3965
3965
TRC=TRC (MIN); TCK=TCK(MIN); Address and control inputs
change only during Active Read or Write commands
DDR200@
CL=2
Max
1400
1715
36
680
225
725
1625
1625
2390
311
3425
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
August 2005
Rev. 4
5
White Electronic Designs Corporation • [phone] • www.wedc.com