W3EG6432S-D4 Datasheet, PDF (7/12 Pages) White Electronic Designs Corporation – 256MB - 32Mx64 DDR SDRAM UNBUFFERED

White Electronic Designs
W3EG6432S-D4
PRELIMINARY
AC OPERATING CONDITIONS
0°C ≤ TA ≤ 70°C, VCC = 2.5V ± 0.2V
AC CHARACTERISTICS
335
262
PARAMETER
SYMBOL MIN MAX MIN MAX
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
CL = 2.5
CL = 2
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
tAC
tCH
tCL
tCK (2.5)
tCK (2)
tDH
tDS
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
tDQSS
tDSS
tDSH
tHP
tHZ
tLZ
tIHF
tISF
tIHS
tISS
tIPW
tMRD
-0.70 +0.70
0.45 0.55
0.45 0.55
6
13
7.5
13
0.45
0.45
1.75
-0.60 +0.60
0.35
0.35
0.45
0.75 1.25
0.2
0.2
tCH, tCL
+0.70
-0.70
0.75
0.75
0.80
0.80
2.2
12
-0.75 +0.75
0.45 0.55
0.45 0.55
7.5
13
7.5
13
0.5
0.5
1.75
-0.75 +0.75
0.35
0.35
0.5
0.75 1.25
0.2
0.2
tCH, tCL
+0.75
-0.75
0.90
0.90
1
1
2.2
15
263/265/202
MIN MAX
-0.75
0.45
0.45
7.5
7.5/10
+0.75
0.55
0.55
13
13
0.5
0.5
1.75
-0.75 +0.75
0.35
0.35
0.5
0.75 1.25
0.2
0.2
tCH, tCL
+0.75
-0.75
0.90
0.90
1
1
2.2
15
UNITS
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
26
26
39, 44
39, 44
23, 27
23, 27
27
22, 23
30
16, 36
16, 36
12
12
12
12
December 2004
Rev. 6
7
White Electronic Designs Corporation • [phone] • www.wedc.com