W3EG6432S-D4 Datasheet, PDF (5/12 Pages) White Electronic Designs Corporation – 256MB - 32Mx64 DDR SDRAM UNBUFFERED

White Electronic Designs
W3EG6432S-D4
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCC = 2.5V ± 0.2V
DDR SDRAM Component Values Only
Parameter
Symbol Conditions
Operating Current
Operating Current
Precharge Power-
Down Standby
Current
Idle Standby
Current
Active Power-Down
Standby Current
Active Standby
Current
Operating Current
Operating Current
Auto Refresh
Current
Self Refresh
Current
Operating Current
One device bank; Active - Precharge;
tRC=tRC(MIN); tCK=tCK(MIN); DQ,DM and DQS
IDD0 inputs changing once per clock cycle; Address
and control inputs changing once every two
cycles.
One device bank; Active-Read-Precharge;
IDD1
Burst = 2; tRC=tRC(MIN);tCK=tCK(MIN); Iout =
0mA; Address and control inputs changing
once per clock cycle.
IDD2P
All device banks idle; Power- down mode;
tCK=tCK(MIN); CKE=(low)
CS# = High; All device banks idle;
IDD2F
tCK=tCK(MIN); CKE = high; Address and other
control inputs changing once per clock cycle.
Vin = Vref for DQ, DQS and DM.
IDD3P
One device bank active; Power-down mode;
tCK(MIN); CKE=(low)
CS# = High; CKE = High; One device
bank; Active-Precharge; tRC=tRAS(MAX);
IDD3N
tCK=tCK(MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address and
other control inputs changing once per clock
cycle.
Burst = 2; Reads; Continous burst; One
IDD4R
device bank active;Address and control inputs
changing once per clock cycle; tCK=tCK(MIN);
Iout = 0mA.
Burst = 2; Writes; Continous burst; One
device bank active; Address and control inputs
IDD4W changing once per clock cycle; tCK=tCK(MIN);
DQ,DM and DQS inputs changing twice per
clock cycle.
IDD5 tRC=tRC(MIN)
IDD6 CKE ≤ 0.2V
Four bank interleaving Reads (BL=4) with auto
IDD7A
precharge with tRC=tRC (MIN); tCK=tCK(MIN);
Address and control inputs change only
during Active Read or Write commands.
DDR333
@CL=2.5
Max
1000
1360
32
400
240
480
1400
1400
2040
32
3280
DDR266
@CL=2
Max
1000
1280
32
360
200
400
1200
1200
1880
32
2800
DDR266
@CL=2.5
Max
1000
1280
32
360
200
400
1200
1200
1880
32
2800
DDR266
@CL=2
Max
1000
1280
32
360
200
400
1200
1200
1880
32
2800
DDR200
@CL=2
Max
Units
1000
mA
1280
mA
32
mA
360
mA
200
mA
400
mA
1200
mA
1200
mA
1880
mA
32
mA
2800
mA
December 2004
Rev. 6
5
White Electronic Designs Corporation • [phone] • www.wedc.com