W3EG128M72ETSU-D3 Datasheet, PDF (7/14 Pages) White Electronic Designs Corporation – 1GB - 128Mx72 DDR SDRAM UNBUFFERED ECC w/PLL

White Electronic Designs
W3EG128M72ETSU-D3
-JD3
-AJD3
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
DDR400: VCC = VCCQ = +2.6V ± 0.1V
AC CHARACTERISTICS
403
335
262
265
202
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
CL = 3
CL = 2.5
CL = 2
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per
access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (1 V/ns)
Address and control input setup time (1 V/ns)
Address and control input hold time (0.5 V/ns)
Address and control input setup time (0.5 V/ns)
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per
access
Data hold skew factor
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command
period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
tAC -0.7 +0.7 -0.7 +0.7 -0.75 +0.75 -0.75 0.75 -0.8 0.8 ns
tCH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK 25
tCL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK 25
tCK (3) 5 7.5 6 13 7.5 13 7.5 13 8 13 ns 38, 43
tCK (2.5) 6 13 7.5 13 7.5 13 7.5/10 13 10 13 ns 38, 43
tCK (2) 7.5 13
ns 37, 42
tDH
0.4
0.45
0.5
0.6
ns 22, 26
tDS
0.4
0.45
0.5
0.6
ns 22, 26
tDIPW 1.75
1.75
1.75
2
ns 26
tDQSCK -0.6 +0.6 -0.60 +0.60 -0.75 +0.75 +0.75 -0.8 +0.8
ns
tDQSH 0.35
0.35
0.35
0.35
tCK
tDQSL 0.35
0.35
0.35
0.35
tCK
tDQSQ
0.40
0.45
0.5
0.5
0.6 ns 22
tDQSS 0.72 1.28 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK
tDSS 0.2
0.2
0.2
0.2
0.2
tCK
tDSH 0.2
0.2
0.2
0.2
0.2
tCK
tHP
tCH,tCL
tCH,tCL
tCH,tCL
tCH,tCL
tCH,tCL
ns 29
tHZ
+0.70
+0.70
+0.75
+0.75
+0.8 ns 16, 36
tLZ -0.70
-0.70
-0.75
-0.75
-0.8
ns 16, 36
tIHF
0.6
0.75
0.90
0.90 1.1 ns 12 ns 12
tISF
0.6
0.75
0.90
0.90
1.1
ns 12
tIHS
0.6
0.80
1
1
1.1
ns 12
tISS
0.6
0.80
1
1
1.1
ns 12
tIPW 2.20
2.2
2.2
2.2
2.2
ns
tMRD
2
12
15
15
16
ns
tQH
tHP
- tQHS
tHP
- tQHS
tHP
- tQHS
tHP
- tQHS
tHP
- tQHS
ns 22
tQHS
0.50
0.60
0.75
0.75
1 ns
tRAS 40 70,000 42 70,000 40 120,000 40 120,000 40 120,000 ns 30
tRAP
15
15
15
20
20
ns
tRC
55
60
60
65
70
ns
tRFC
70
72
75
72
75
tRCD
15
15
15
20
20
tRP
15
15
15
20
20
tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1
tRPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6
tRRD
10
12
15
15
15
tWPRE 0.25
0.25
0.25
0.25
0.25
tWPRES
0
0
0
0
0
ns 41
ns
ns
tCK 36
tCK 36
ns
tCK
ns 17, 19
January 2005
Rev. 0
7
White Electronic Designs Corporation • [phone] • www.wedc.com