W3EG128M72ETSU-D3 Datasheet, PDF (10/14 Pages) White Electronic Designs Corporation – 1GB - 128Mx72 DDR SDRAM UNBUFFERED ECC w/PLL

White Electronic Designs
W3EG128M72ETSU-D3
-JD3
-AJD3
ADVANCED
33. The voltage levels used are derived from a mini-mum VCC level and the referenced
test load. In practice, the voltage levels obtained from a properly terminated bus will
provide significantly different voltage values.
34. VIH overshoot: VIH (MAX) = VCCQ + 1.5V for a pulse width < 3ns and the pulse width
can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a
pulse width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate.
35. VCC and VCCQ must track each other.
36. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will
prevail over tDQSCK (MIN) + tRPRE (MAX) condition.
37. tRPST end point and tRPRE begin point are not referenced to a specific voltage level
but specify when the device output is no longer driving (tRPST), or begins driving
(tRPRE).
38. During initialization, VCCQ, VTT, and VREF must be equal to or less than VCC + 0.3V.
Alternatively, VTT may be 1.35V maximum during power up, even if VCC/VCCQ
are 0V, provided a minimum of 42 0 of series resistance is used between the VTT
supply and the input pin.
39. The current part operates below the slowest JEDEC operating frequency of 83
MHz. As such, future die may not reflect this option.
40. Random addressing changing and 50 percent of data changing at every transfer.
41. Random addressing changing and 100 percent of data changing at every transfer.
42. CKE must be active (high) during the entire time a refresh command is executed.
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until tREF later.
43. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level.
IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to
remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is “worst case.”
44. Whenever the operating frequency is altered, not including jitter, the DLL is required
to be reset. This is followed by 200 clock cycles (before READ commands).
45. Leakage number reflects the worst case leakage possible through the module pin,
not what each memory device contributes.
46. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or
LOW.
47. The 403 speed grade will operate with tRAS (MIN) = 40 ns and tRAS (MAX) =
120,000ns at any slower frequency.
January 2005
Rev. 0
10
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