W3HG64M72EER-AD7 Datasheet, PDF (6/14 Pages) White Electronic Designs Corporation – 512MB - 64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM

White Electronic Designs
W3HG64M72EER-AD7
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only; TA = 0°C, VCC = 1.9V
Symbol Parameter
Condition
806
667
534
403
Unit
ICCO*
Operating one bank
active-precharge;
tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is
HIGH between valid commands; Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
TBD
810
720
720
mA
Operating one
ICC1* bank active-read-
precharge;
IOUT = OmA; BL = 4; CL = CL(ICC); tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS
MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are SWITCHING; Data bus inputs are SWITCHING; Data
pattern is sames as ICC4W.
TBD
945
855
810
mA
ICC2P**
Precharge power-
down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING
TBD
45
45
45
mA
ICC2Q**
Precharge quite
standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH; CS# is HIGH; Other control
and address bus inputs are STABLE; Data bus inputs are FLOATING
TBD
450
360
315
mA
ICC2N**
Precharge standby
current;
All banks idle; tCK = tCK(ICC); CKE is HIGH; CS# is HIGH; Other control
and address bus inputs are STABLE; Data bus inputs are SWITCHING
TBD
495
405
360
mA
ICC3P**
Active power-down
current;
All banks open; tCK = tCK(ICC), CKE is LOW;
Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
Fast PDN Exit
MRS(12) = 0
Slow PDN Exit
MRS(12) = 1
TBD
315
270
225
mA
TBD
90
90
90
mA
ICC3N**
Active standby
current;
All banks open; tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE
is HIGH, CS# is HIGH between valid commands; Other control and
TBD
585
495
405
mA
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
All banks open; Continuous burst writes; BL = 4; CL = CL(ICC); AL =
ICC4W*
Operating burst
write current;
0; tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is
HIGH between valid commands; Address bus inputs are SWITCHING;
TBD
1,395 1,170 990
mA
Data bus inputs are SWITCHING
ICC4R*
Operating burst
read current;
All banks open; Continuous burst reads; TOUT = OmA; BL = 4; CL =
CL(ICC); AL = 0; tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is
HIGH, CS# is HIGH between valid commands; Address bus inputs are
TBD
1,575 1,305 1,035
mA
SWITCHING; Data pattern is same as ICC4W.
ICC5**
Burst auto refresh
current;
tCK = tCK(ICC); Refresh command at every tRC(ICC) interval; CKE is HIGH;
CS# is HIGH between valid commands; Other control and address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
TBD
1,890 1,800 1,710
mA
CK and CK# at OV; CKE < 0.2V; Other control
ICC6** Self refresh current; and address bus inputs are FLOATING; Data
bus inputs are FLOATING
Normal
TBD
45
45
45
mA
Operating bank
ICC7* interleave read
curent;
All bank interleaving reads; IOUT = OmA; BL = 4; CL = CL(ICC); AL
= tRCD(ICC) - 1*tCK(ICC); tCK = tCK(ICC); tRC = tRC(ICC); tRRD = tRRD MIN(ICC)
= 1*tCK(ICC); CKE is HIGH; CS# is HIGH between valid commands;
Address bus inputs are STABLE during DESELECTs; Data bus inputs
are SWITCHING
TBD 2,520 2,340 2,070 mA
Notes:
ICC specification is based on MICRON components. Other DRAM manufacturers specification may be different.
* Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P ( CKE LOW) mode.
** Value calculated reflects all module ranks in this operating condition.
December 2005
Rev. 1
6
White Electronic Designs Corporation • [phone] • www.wedc.com