W3EG264M72AFSRXXXD3 Datasheet, PDF (6/13 Pages) White Electronic Designs Corporation – 1GB - 2x64Mx72 DDR SDRAM REGISTERED ECC w/PLL, FBGA

White Electronic Designs ^{W3EG264M72AFSRxxxD3}
ADVANCED
Parameter
Operating Current
Operating Current
Precharge Power-
Down Standby Current
Idle Standby Current
Active Power-Down
Standby Current
Active Standby Current
Operating Current
Operating Current
Auto Refresh Current
Self Refresh Current
Operating Current
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ +70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V.
Includes PLL and register power
Rank 1
Symbol Conditions
IDD0 One device bank; Active - Precharge; tRC
= tRC (MIN); tCK = tCK (MIN); DQ,DM and
DQS inputs changing once per clock cycle;
Address and control inputs changing once
every two cycles.
IDD1 One device bank; Active-Read-Precharge
Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN);
lOUT = 0mA; Address and control inputs
changing once per clock cycle.
IDD2P All device banks idle; Power-down mode;
tCK = tCK (MIN); CKE = (low)
IDD2F CS# = High; All device banks idle;
tCK = tCK (MIN); CKE = High; Address
and other control inputs changing once
per clock cycle. VIN = VREF for DQ, DQS
and DM.
IDD3P One device bank active; Power-Down
mode; tCK (MIN); CKE = (low)
IDD3N CS# = High; CKE = High; One device
bank; Active-Precharge;tRC = tRAS (MAX);
tCK = tCK (MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address
and other control inputs changing once per
clock cycle.
IDD4R Burst = 2; Reads; Continuous burst; One
device bank active; Address and control
inputs changing once per clock cycle; tCK =
tCK (MIN); lOUT = 0mA.
IDD4W Burst = 2; Writes; Continuous burst; One
device bank active; Address and control
inputs changing once per clock cycle;
tCK = tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle.
IDD5 tRC = tRC (MIN)
IDD6 CKE ≤ 0.2V
IDD7A Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC (MIN);
tCK=tCK(MIN); Address and control inputs
change only during Active Read or Write
commands.
DDR333@CL=2.5
Max
4995
5805
144
2110
1080
2470
5895
5625
7370
419
10125
DDR266:@CL=2, 2.5
Max
4635
5265
144
1930
900
2110
5085
4815
6650
419
8685
DDR200@CL=2
Max
4635
5265
144
1930
900
2110
5085
4815
6650
419
8685
Units
mA
Rank 2
Standby
State
IDD3N
mA
IDD3N
rnA
IDD2P
mA
IDD2F
mA
IDD3P
mA
IDD3N
mA
IDD3N
rnA
IDD3N
mA
IDD3N
mA
IDD6
mA
IDD3N
November 2004
Rev. 1
6
White Electronic Designs Corporation • [phone] • www.wedc.com