W3EG7263S-D3 Datasheet, PDF (5/13 Pages) White Electronic Designs Corporation – 512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL

White Electronic Designs
W3EG7263S-D3
-JD3
-AJD3
PRELIMINARY
Parameter
Operating Current
Operating Current
Precharge Power-
Down Standby Current
Idle Standby Current
Active Power-Down
Standby Current
Active Standby Current
Operating Current
Operating Current
Auto Refresh Current
Self Refresh Current
Operating Current
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C £ TA £ +70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V.
Includes DDR SDRAM components and PLL and Register
Rank 1
Symbol Conditions
IDD0 One device bank; Active - Precharge;
tRC = tRC (MIN); tCK = tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control inputs
changing once every two cycles.
IDD1 One device bank; Active-Read-
Precharge Burst = 2; tRC = tRC (MIN);
tCK = tCK (MIN); lOUT = 0mA; Address
and control inputs changing once per
clock cycle.
IDD2P All device banks idle; Power-down
mode; tCK = tCK (MIN); CKE = (low)
IDD2F CS# = High; All device banks idle;
tCK = tCK (MIN); CKE = High; Address
and other control inputs changing once
per clock cycle. VIN = VREF for DQ, DQS
and DM.
IDD3P One device bank active; Power-Down
mode; tCK (MIN); CKE = (low)
IDD3N CS# = High; CKE = High; One device
bank; Active-Precharge;tRC = tRAS
(MAX); tCK = tCK (MIN); DQ, DM and
DQS inputs changing twice per clock
cycle; Address and other control inputs
changing once per clock cycle.
IDD4R Burst = 2; Reads; Continuous burst;
One device bank active; Address and
control inputs changing once per clock
cycle; tCK = tCK (MIN); lOUT = 0mA.
IDD4W Burst = 2; Writes; Continuous burst;
One device bank active; Address and
control inputs changing once per clock
cycle; tCK = tCK (MIN); DQ,DM and DQS
inputs changing once per clock cycle.
IDD5
tRC = tRC (MIN)
IDD6 CKE £ 0.2V
IDD7A Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC (MIN);
tCK=tCK(MIN); Address and control
inputs change only during Active Read
or Write commands.
DDR333@CL=2.5
Max
TBD
DDR266:@CL=2, 2.5
Max
1715
DDR200@CL=2 S
Max
1715
TBD
2255
2255
TBD
54
54
TBD
671
671
TBD
540
540
TBD
1121
1121
TBD
2795
2795
TBD
2795
2795
TBD
3281
3281
TBD
365
365
TBD
5315
5315
Units
mA
mA
rnA
mA
mA
mA
mA
rnA
mA
mA
mA
Rank 2
Standby
State
IDD3N
IDD3N
IDD2P
IDD2F
IDD3P
IDD3N
IDD3N
IDD3N
IDD3N
IDD6
IDD3N
April 2004
Rev. # 2
5
White Electronic Designs Corporation • [phone] • www.wedc.com