W3EG6464S-JD3 Datasheet, PDF (5/12 Pages) White Electronic Designs Corporation – 512MB - 64Mx64 DDR SDRAM UNBUFFERED

White Electronic Designs
W3EG6464S-JD3-D3
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Includes DDR SDRAM component only
Parameter
Operating Current
Symbol
IDD0
Operating Current
IDD1
Precharge Power-
IDD2P
Down Standby
Current
Idle Standby Current IDD2F
Active Power-Down IDD3P
Standby Current
Active Standby
IDD3N
Current
Operating Current
IDD4R
Operating Current
IDD4W
Auto Refresh Current IDD5
Self Refresh Current IDD6
Operating Current
IDD7A
Conditions
One device bank; Active - Precharge; tRC=tRC
(MIN); tCK=tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle; Address and control
inputs changing once every two cycles.
One device bank; Active-Read-Precharge Burst
= 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA;
Address and control inputs changing once per
clock cycle.
All device banks idle; Power-down mode; tCK=tCK
(MIN); CKE=(low)
CS# = High; All device banks idle; tCK=tCK (MIN);
CKE = high; Address and other control inputs
changing once per clock cycle. VIN = VREF for DQ,
DQS and DM.
One device bank active; Power-Down mode; tCK
(MIN); CKE=(low)
CS# = High; CKE = High; One device bank; Active-
Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM
and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once
per clock cycle.
Burst = 2; Reads; Continuous burst; One device
bank active; Address and control inputs changing
once per clock cycle; TCK= TCK (MIN); lOUT = 0mA.
Burst = 2; Writes; Continuous burst; One device
bank active; Address and control inputs changing
once per clock cycle; tCK=tCK (MIN); DQ,DM and
DQS inputs changing once per clock cycle.
tRC = tRC (MIN)
CKE ≤ 0.2V
Standard
Low Power
Four bank interleaving Reads (BL=4) with auto
precharge with tRC=tRC (MIN); tCK=tCK (MIN);
Address and control inputs change only during
Active Read or Write commands.
DDR266@CL=2
Max
1320
1520
48
400
400
760
1760
2000
2480
40
25
3840
DDR266@CL=2.5
Max
1320
1520
48
400
400
760
1760
2000
2480
40
25
3840
DDR266 &
200@CL=2
Max
1320
1520
48
400
400
760
1760
2000
2480
40
25
3840
Units
mA
mA
rnA
mA
mA
mA
mA
rnA
mA
mA
mA
May 2005
Rev. 3
5
White Electronic Designs Corporation • [phone] • www.wedc.com