W3EG6464S-JD3 Datasheet, PDF (1/12 Pages) White Electronic Designs Corporation – 512MB - 64Mx64 DDR SDRAM UNBUFFERED

White Electronic Designs
W3EG6464S-JD3-D3
PRELIMINARY*
512MB – 64Mx64 DDR SDRAM UNBUFFERED
FEATURES
Double-data-rate architecture
DDR200 and DDR266
• JEDEC design specification
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Serial presence detect
Power supply: VCC: 2.5V ± 0.20V
JEDEC standard 184 pin DIMM package
• Package height option:
JD3: 30.48mm (1.20")
DESCRIPTION
The W3EG6464S is a 64Mx64 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. The module consists of eight 64Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
NOTE: Consult factory for availability of:
• Lead-Free Products
• Vendor source control options
• Industrial temperature options
Clock Speed
CL-tRCD-tRP
OPERATING FREQUENCIES
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR266 @CL=2
133MHz
2-3-3
DDR200 @CL=2
100MHz
2-2-2
May 2005
Rev. 3
1
White Electronic Designs Corporation • [phone] • www.wedc.com