W3H64M72E-XSBX Datasheet, PDF (26/30 Pages) White Electronic Designs Corporation – 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package

White Electronic Designs
W3H64M72E-XSBX
ADVANCED*
AC TIMING PARAMETERS (continued)
-55°C ≤ TA < +125°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V
Parameter
Symbol
533Mbs CL4
Min
Max
400Mbs CL3
Unit
Min
Max
DQ hold skew factor
t_QHS
-
400
-
450
ps
DQ output access time from CK/CK#
t_AC
-500
+500
-600
+600
ps
Data-out high impedance window from CK/CK#
DQS Low-Z window from CK/CK#
t_HZ
tLZ1
tAC(MN)
tAC(MAX)
tAC(MAX)
tAC(MN)
tAC(MAX)
ps
tAC(MAX)
ps
DQ Low-Z window from CK/CK#
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
tLZ2
2*tAC(MN)
tAC(MAX)
2*tAC(MN)
tAC(MAX)
ps
t_DSa
350
400
ps
t_DHa
350
400
ps
t_DSb
100
150
ps
t_DHb
225
275
ps
t_DIPW
0.35
0.35
ps
Data hold skew factor
t_QHS
400
450
ps
DQ-DQS hold, DQS to first DQ to go nonvalid, per access
t_QH
tHP - tQHS
tHP - tQHS
ps
Data valid output window (DVW)
t_DVW
tQH - tDQSQ
tQH - tDQSQ
ns
DQS input high pulse width
t_DQSH
0.35
0.35
tCK
DQS input low pulse width
t_DQSL
0.35
0.35
tCK
DQS output access time fromCK/CK#
t_DQSCK
-450
+450
-500
+500
ps
DQS falling edge to CK rising - setup time
t_DSS
0.2
0.2
tCK
DQS falling edge from CK rising - hold time
t_DSH
0.2
0.2
tCK
DQS-DQ skew, DOS to last DQ valid, per group, per access ^tDQSQ
300
350
ps
DQS read preamble
DQS read postamble
DQS write preamble setup time
t_RPRE
0.9
1.1
0.9
1.1
tCK
t_RPST
0.4
0.6
0.4
0.6
tCK
t_WPRES
0
0
ps
DQS write preamble
t_WPRE
0.25
0.25
tCK
DQS write postamble
t_WPST
0.4
0.6
0.4
0.6
tCK
Positive DQS latching edge to associated clock edge
t_DQSS
-0.25
0.25
-0.25
0.25
tCK
Write command to first DQS latching transition
WL-TDQSS
WL+TDQSS
WL-TDQSS
WL+TDQSS
tCK
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
26
White Electronic Designs Corporation • [phone] • www.wedc.com