W3E32M72S-XBX Datasheet, PDF (14/19 Pages) White Electronic Designs Corporation – 32Mx72 DDR SDRAM

White Electronic Designs
W3E32M72S-XBX
NOTES:
1. All voltages referenced to VSS.
2. Tests for AC timing, ICC, and electrical AC and DC characteristics may be
conducted at nominal reference/supply voltage levels, but the related specifications
and device operation are guaranteed for the full voltage range specified.
3. Outputs measured with equivalent load:
VTT
Output
(VOUT)
50Ω
Reference
Point
30pF
4. AC timing and ICC tests may use a VIL-to-VIH swing of up to 1.5V in the test
environment, but input timing is still referenced to VREF (or to the crossing point for
CK/CK#), and parameter specifications are guaranteed for the specified AC input
levels under normal use conditions. The minimum slew rate for the input signals
used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard
(i.e., the receiver will effectively switch as a result of the signal crossing the AC
input level, and will remain in that state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
6. VREF is expected to equal VCCQ/2 of the transmitting device and to track variations
in the DC level of the same. Peak-to-peak noise (noncommon mode) on VREF may
not exceed ±2 percent of the DC value. Thus, from VCCQ/2, VREF is allowed ±25mV
for DC error and an additional ±25mV for AC noise. This measurement is to be
taken at the nearest VREF by-pass capacitor.
7. VTT is not applied directly to the device. VTT is a system supply for signal
termination resistors, is expected to be set equal to VREF and must track variations
in the DC level of VREF.
8. VID is the magnitude of the difference between the input level on CK and the input
level on CK#.
9. The value of VIX and VMP are expected to equal VCCQ/2 of the transmitting device
and must track variations in the DC level of the same.
10. ICC is dependent on output loading and cycle rates. Specified values are obtained
with minimum cycle time with the outputs open.
11. Enables on-chip refresh and address counters.
12. ICC specifications are tested after the device is properly initialized, and is averaged
at the defined cycle rate.
13. This parameter is not tested but guaranteed by design. tA = 25°C, F= 1 MHz
14. For slew rates less than 1V/ns and greater than or equal to 0.5 V.ns. If the slew
rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50 ps per
each 100mV/ns reduction in slew rate from the 500mV/ns. tIH has 0ps added, that
is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain.
15. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at
which CK# and CK# cross; the input reference level for signals other than CK/CK#
is VREF.
16. Inputs are not recognized as valid until VREF stabilizes. Once initialized, including
SELF REFRESH mode, VREF must be powered within specified range. Exception:
during the period before VREF stabilizes, CKE ≤ 0.3 x VCCQ is recognized as LOW.
17. The output timing reference level, as measured at the timing reference point
indicated in Note 3, is VTT.
18. tHZ and tLZ transitions occur in the same access time windows as valid data
transitions. These parameters are not referenced to a specific voltage level, but
specify when the device output is no longer driving (HZ) or begins driving (LZ).
19. The intent of the Don't Care state after completion of the postamble is the DQS-
driven signal should either be high, low, or high-Z and that any signal transition
within the input switching region must follow valid input requirements. That is, if
DQS transitions high (above VIHDC(MIN) then it must not transition low (below
VIHDC) prior to tDQSH(MIN).
20. This is not a device limit. The device will operate with a negative value, but system
performance could be degraded due to bus turnaround.
21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE
command. The case shown (DQS going from High-Z to logic LOW) applies when
no WRITEs were previously in progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time, depending on tDQSS.
22. MIN (tRC or tRFC) for ICC measurements is the smallest multiple of tCK that meets
the minimum absolute value for the respective parameter. tRAS (MAX) for ICC
measurements is the largest multiple of tCK that meets the maximum absolute
value for tRAS.
23. The refresh period 64ms. (32ms for Military grade) This equates to an average
refresh rate of 7.8125µs. However, an AUTO REFRESH command must be
asserted at least once every 70.3µs; (35µs for Military grade) burst refreshing or
posting by the DRAM controller greater than eight refresh cycles is not allowed.
24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this
maximum amount for any given device.
25. The valid data window is derived by achieving other specifications - tHP (tCK/2),
tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly porportional
with the clock duty cycle and a practical data valid window can be derived. The
clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain
when operating beyond a 45/55 ratio. The data valid window derating curves are
provided below for duty cycles ranging between 50/50 and 45/55.
FIGURE A – FULL DRIVE PULL-DOWN
CHARACTERISTICS
160
Maximum
140
120
Nominal high
100
80
Nominal low
60
Minimum
40
20
0
0.0
0.5
1.0
1.5
2.0
2.5
VOUT (V)
FIGURE B – FULL DRIVE PULL-UP
CHARACTERISTICS
0
-20
Minimum
-40
-60
Nominal low
-80
-100
-120
Nominal high
-140
-160
-180
Maximum
-200
0.0
0.5
1.0
1.5
2.0
2.5
VCCQ - VOUT (V)
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 2
14
White Electronic Designs Corporation • [phone] • www.wedc.com