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VG37648041AT Datasheet, PDF (76/86 Pages) Vanguard International Semiconductor – 256M:x4, x8, x16 CMOS Synchronous Dynamic RAM
VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
INITIALIZE AND LOAD MODE REGISTERS
VDD
VDDQ
VTT
(system*)
VREF
CLK#
CLK
tVTD
CKE
LVCMOS LOW LEVEL
tCK
tCH tCL
tIS tIH
COMMAND
NOP
PRE
LMR
LMR
PRE
AR
AR
ACT
DM
A0,A9,
A11,A12
A10
BA0,BA1
DQS
DQ
tIS tIH
CODE CODE
RA
ALL BANKS
ALL BANKS
CODE CODE
RA
tIS tIH tIS tIH
tIS tIH
BA0=H,
BA0=L,
BA
BA1=L
BA1=L
High-Z
High-Z
T=200 µs
Power-up:
VDD and
CLK stable
tMRD
Load
200
cycles
tRP
of CLK...
tRC
tRC
Extended
Mode
Load
Register
Base
Mode
Register
DONT’ CARE
UNDEFINED
•=VTT is not applied directly to the device, however tVTD must be greater than or equal to
zero to avoid device latch-up.
••=t MRD is required before any command can be applied, and 200 cycles of CLK are required before a
READ command can be applied.
Document : 1G5-0157
Rev.1
Page 76