VG37648041AT Datasheet, PDF (25/86 Pages) Vanguard International Semiconductor – 256M:x4, x8, x16 CMOS Synchronous Dynamic RAM

VIS
Preliminary
VG37648041AT
256M:x4, x8, x16
CMOS Synchronous Dynamic RAM
CLK#
CLK
COMMAND
READ
NOP
ADDRESS
DQS
DQ
Bank,
Col n
CL=2
READ
Bank,
Col b
NOP
DO
n
NOP
NOP
DO
b
CLK#
CLK
COMMAND
READ
NOP
ADDRESS
DQS
DQ
Bank,
Col n
CL=2.5
READ
Bank,
Col b
NOP
DO
n
NOP
NOP
DO
b
DONT’ CARE
UNDEFINED
Do n(or b)= Data Out from column n (or column b)
Burst Length= 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first)
3 subsequent elements of Data Out appear in the programmed order following DO n
3 (or 7) subsequent elements of Data Out appear in the programmed order following DO b
Figure 8a
CONSECUTIVE READ BURSTS - REQUIRED CAS LATENCIES
Document : 1G5-0157
Rev.1
Page 25