VG4632321A Datasheet, PDF (6/81 Pages) Vanguard International Semiconductor – 524,288x32x2-Bit CMOS Synchronous Graphic RAM

VIS
Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
Commands
1 BankActivate & Masked Write Disable command
(RAS = ”L”, CAS = ”H”, WE = ”H”, DSF = ”L”, BS = Bank, A0-A10 = Row Address)
The BankActivate command activates the idle bank designated by the BS (Bank Select) signal. By
latching the row address on A0 to A10 at the time of this command, the selected row access is initiated.
The read or write operation in the same bank can occur after a time delay of t_RCD(min.) from the time of
bank activation. A subsequent BankActivate command to a different row in the same bank can only be
issued after the previous active row has been precharged (refer to the following figure). The minimum
time interval between successive BankActivate commands to the same bank is defined by t_RC(min.).
The SGRAM has two internal banks on the same chip and shares part of the internal circuitry to reduce
chip area, therefore it restricts the back-to-back activation of both banks. t_RRD(min.) specifies the
minimum time required between activating different banks. After this command is used, the Write
command and the Block Write command perform the no mask write operation.
T0
T1
T2
T3
Tn+3
Tn+4
Tn+5
Tn+6
CLK
ADDRESS
Bank A
Row Addr.
Bank A
Col Addr.
Bank A
Row Addr.
COMMAND
RAS-CAS delay (t_RCD)
Bank A
Activate
NOP
NOP
R/W A with
AutoPrecharge
RAS-RAS delay time (t_RRD)
Bank B
Activate
NOP
NOP
RAS Cycle time (t_RC)
: “H” or “L”
AutoPrecharge
Begin
BankActivate Command Cycle (Burst Length = n, CAS Latency = 3)
Bank A
Row Addr.
Bank A
Activate
2 BankActivate & Masked Write Enable command (refer to the above figure)
(RAS = ”L”, CAS = ”H”, WE = ”H”, DSF = ”H”, BS = Bank, A0-A10 = Row Address)
The BankActivate command activates the idle bank designated by BS signal. After this command is
performed, the Write command and the Block Write command perform the masked write operation. In
the masked write and the masked block write functions, the I/O mask data that was stored in the write
mask register is used.
3 BankPrecharge command
(RAS = ”L”, CAS = ”H”, WE = ”L”, DSF = ”L”, BS = Bank, A8 = ”L”, A0-A7,A9,A10 = Don’t care)
The BankPrecharge command precharges the bank designated by BS signal. The precharged
bank is switched from the active state to the idle state. This command can be asserted anytime after
t_RAS(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any
bank can be active is specified by t_RAS(max.). Therefore, the precharge function must be performed in
any active bank within t_RAS(max.). At the end of precharge, the precharged bank is still the idle state and
ready to be activated again.
4 PrechargeAll command
(RAS = ”L”, CAS = ”H”, WE = ”L”, DSF = ”L”, BS = Don’t care, A8 = ”H”, A0-A7,A9,A10 = Don’t care)
The PrechargeAll command precharges both banks simultaneously. Even if both banks are not in
the active state, the PrechargeAll command can be issued. Both banks are then switched to the idle
state.
5 Read command
(RAS = ”H”, CAS = ”L”, WE = ”H”, DSF = ”L”, BS = Bank, A8 = ”L”, A0-A7 = Column Address, A9,A10 = Don’t
care)
Document:
Rev.1
Page 6