VG4632321A Datasheet, PDF (1/81 Pages) Vanguard International Semiconductor – 524,288x32x2-Bit CMOS Synchronous Graphic RAM

VIS
Overview
Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
The VG4632321A SGRAM is a high-speed CMOS synchronous graphic RAM containing 32M bits. It is
internally configured as a dual 512K x 32 DRAM with a synchronous interface (all signals are registered on
the positive edge of the clock signal, CLK). Each of the 512K x 32 bit bank is organized as 2048 rows by 256
columns by 32 bits. Read and write accesses to the SGRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed sequence. Accesses begin
with the registration of a BankActivate command which is then followed by a Read or Write command.
The VG4632321A provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with
burst termination option. An Auto Precharge function may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy
to use. In addition, it features the write per bit and the masked block write functions.
By having a programmable Mode register and special mode register, the system can choose the best
suitable modes to maximize its performance. These devices are well suited for applications requiring high
memory bandwidth, and when combined with special graphics functions result in a device particularly well
suited to high performance graphics applications.
Pin Assignment (Top View)
Features
• Fast access time from clock: 4.5/5/5.5/6/7ns
• Fast clock rate: 222/200/183/166/143MHz
• Fully synchronous operation
• Internal pipelined architecture
• Dual internal banks(512K x 32-bit x 2-bank)
• Programmable Mode and Special Mode registers
- CAS Latency: 1, 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst Read Single Write
- Load Color or Mask register
• Burst stop function
• Individual byte controlled by DQM0-3
• Block write and write-per-bit capability
• Auto Refresh and Self Refresh
• 2048 refresh cycles/32ms
• Single + 3.3V ±0.3V power supply
• Interface: LVTTL
• JEDEC 100-pin Plastic QFP package
DQ3 1
V_{DDQ 2}
DQ4 3
DQ5 4
V_{SSQ 5}
DQ6 6
DQ7 7
V_{DDQ 8}
DQ16 9
DQ17 10
V_SSQ 11
DQ18 12
DQ19 13
V_{DDQ 14}
V_{DD 15}
V_{SS 16}
DQ20 ₁₇
DQ21 18
V_SSQ 19
DQ22 20
DQ23 21
V_{DDQ 22}
DQM0 23
DQM2 24
WE 25
CAS 26
RAS 27
CS 28
BS 29
A9 30
Key Specifications
VG4632321A
t_CK
Clock Cycle time(min.)
t_RAS
Row Active time(min.)
t_AC
Access time from CLK(max.)
t_RC
Row Cycle time(min.)
-4.5/-5/-5.5/-6/-7
4.5/5/5.5/6/7 ns
40/40/40/42/42 ns
4/4.5/5/5.5/6 ns
55/55/56.5/60/62 ns
80 DQ28
79 VDDQ
78 _DQ27
77 _DQ26
76
75
V_SSQ
DQ25
74 DQ24
73
72
V_DDQ
DQ15
71 _DQ14
70 _VSSQ
69 DQ13
68 DQ12
67 _VDDQ
66 V_SS
65 V_DD
64 DQ11
63 DQ10
62 V_SSQ
61 _DQ9
60 DQ8
59
58
V_DDQ
NC
57 DQM3
56 DQM1
55 CLK
54 CKE
53 DSF
52 NC
51 A8/AP
Document:
Rev.1
Page 1