VG36128401BT Datasheet, PDF (4/68 Pages) Vanguard International Semiconductor – CMOS Synchronous Dynamic RAM

VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Pin Function
Symbol
CLK
CKE
/CS
/RAS, /CAS,
/WE
A0 - A13
BA0,BA1
DQM, UDQM ,
LDQM
DQ0 - DQ15
V_DD, V_SS
V_DDQ, V_SSQ
Input
Function
Input Maste Clock: Other inputs signals are referenecd to the CLK rising edge.
Input
Input
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals,
device input buffers and output drivers. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-
DOWN (row ACTIVE in any bank).
Chip Select: /CS enables (registered LOW) and disables (registered HIGH) the com-
mand decoder. All commands are masked when /CS is registered HIGH. /CS provides
for external bank selection on systems with multiple banks. /CS is considered part of
the command code.
Input Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being
entered.
Input
Address Inputs: Provide the row address for ACTIVE commands, and the column
address and AUTO PRECHARGE bit for READ/WRITE commands, to select one loca-
tion out of the memory array in the respective bank.
The row address is specified by A0-A11.
The column address is specified by A0-A9, A11 (X4) / A0-A9 (X8) / A0-A8 (X16)
Input Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
Input Din Mask / Output Disable: When DQM is high in burst write, Din for the current cycle is
masked. When DQM is is high in burst read, Dout is disable at the next but one cycle.
I/O Data Input / Output: Data bus.
Supply Power Supply for the memory array and peripheral circuitry.
Supply Power Supply are supplied to the output buffers only.
Document :1G5-0183
Rev.1
Page 4