VG3617161DT Datasheet, PDF (20/70 Pages) Vanguard International Semiconductor – 16Mb CMOS Synchronous Dynamic RAM

VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
8.AUTO PRECHARGE
During a READ or WRITE command cycle, A10 controls whether AUTO PRECHARGE is selected. If A10 is
high in the READ or WRITE command (READ with AUTO PRECHARGE command or WRITE with AUTO PRE-
CHARGE command), AUTO PRECHARGE is selected and precharging begins automatically after the burst
access.
In the WRITE cycle, t_DAL(min.) must be satisfied to assert the next active command to the bank being pre-
charged.
When using AUTO PRECHARGE in the READ cycle, knowing when the PRECHARGE starts is important
because the t_RAS must be satisfied. Once AUTO PRECHARGE has started, an active command to the bank can
be asserted after t_RP(min.) has been satisfied.
The timing at which the AUTO PRECHARGE cycle begins depends both on the CAS Iatency programmed
into the mode register and on whether the cycle is READ or WRITE.
8.1 READ with AUTO PRECHARGE
During a READA cycle, the AUTO PRECHARGE begins one clock earlier(CAS Iatency of 2) or two
clocks earlier(CAS Iatency of 3) than the last data word output.
READ with AUTO PRECHARGE
T0
T1
CLK
Command
READA B
CAS latency=2
DQ
Command
READA B
CAS latency=3
DQ
Remark READA means READ with AUTO PRECHARGE
Burst lengh=4
T2
T3
T4
T5
T6
T7
T8
Auto precharge starts
QB0
QB1
QB2
QB3
Hi-Z
Auto precharge starts
QB0
QB1
Hi-Z
QB2
QB3
Document:1G5-0160
Rev.1
Page 20