VSC7182 Datasheet, PDF (7/18 Pages) Vitesse Semiconductor Corporation – Quad Transceiver for Gigabit Ethernet and Fibre Channel

® VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7182
Quad Transceiver
for Gigabit Ethernet and Fibre Channel
Figure 4: Receive Timing Waveforms
RCi0
(RCM=LOW)
RCi1
RCi0
(RCM=HIGH)
RCi1
RXi[0:9]
VALID
T₁
T₂
VALID
VALID
SYNi
+/-RXi
RCi1
RXi0 RXi1 RXi2
R_LAT
Table 4: Receive Timing Waveforms
Parameters
Description
Min Typ Max Units
Conditions
T₁
T₂
T₃
T₄
T_R, T_F
R_LAT
T_LOCK
TTL outputs valid prior to RCi1/RCi0 rise
TTL outputs valid after RCi1 or RCi0 rise
Delay between rising edge of RCi1 to
rising edge of RCi0
Period of RCi1 and RCi0
4.0
3.0
TBD
3.0
2.0
TBD
10 x T_RX
-500
1.98 x
T_RFC
TTL Output rise and fall time
—
Latency from serial bit RXi0 to rising edge
RCi1
Data acquisition lock time⁽¹⁾
12bc +
2.77ns
—
—
—
—
—
—
—
10 x T_RX
+500
2.02 x
T_RFC
2.4
13bc +
7.28ns
1400
ns
ns
ps
ps
ns
bit
times
At 1.0625Gb/s
At 1.25Gb/s
At 1.36Gb/s
At 1.0625Gb/s
At 1.25Gb/s
At 1.36Gb/s
T_RX is the bit period of the
incoming data on RXi.
Whether or not locked to
serial data.
Between V_IL(MAX) and
V_IH(MIN), into 10 pf load.
bc = bit clock
ns = nanosecond
8B/10B IDLE pattern.
Tested on a sample basis.
NOTE: (1) Probability of recovery for data acquisition is 95% per Section 5.3 of FC-PH rev. 4.3.
G52307-0, Rev 2.2
10/10/00
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: [phone] • Email: [e-mail]
Internet: www.vitesse.com
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