VSC7182 Datasheet, PDF (12/18 Pages) Vitesse Semiconductor Corporation – Quad Transceiver for Gigabit Ethernet and Fibre Channel

® VITESSE
SEMICONDUCTOR CORPORATION
Quad Transceiver
for Gigabit Ethernet and Fibre Channel
Advance Product Information
VSC7182
Table 7: Pin Descriptions
Pin
N1, N2, N3
N4, M1, M2,
M3, M4, L1
L2
J1, J2, J3
J4, H1, H2
H3, H4, G1
G2
G16, G15, G14
H17, H16, H15
H14, J17, J16
J15
L17, L16, L15
L14, M17, M16
M15, M14, N17
N16
R2
P3
R1
P2
P16
P14
K1, F1
K17, P17
P1
Name
TA0, TA1, TA2
TA3, TA4, TA5
TA6, TA7, TA8
TA9
TB0, TB1, TB2
TB3, TB4, TB5
TB6, TB7, TB8
TB9
TC0, TC1, TC2
TC3, TC4, TC5
TC6, TC7, TC8
TC9
TD0, TD1, TD2
TD3, TD4, TD5
TD6, TD7, TD8
TD9
RFC+
RFC-
RFCT
RFCM
RFCO0
RFCO1
TCA, TCB
TCC, TCD
LTCN
Description
INPUT - TTL: 10-Bit Transmit Bus for Channel A. Parallel data on this bus is latched
on the rising edge of RFC, TCC or TCA. TA0 is transmitted first.
INPUT - TTL: 10-Bit Transmit Bus for Channel B. Parallel data on this bus is latched
on the rising edge of RFC, TCC or TCB. TB0 is transmitted first.
INPUT - TTL: 10-Bit Transmit Bus for Channel C. Parallel data on this bus is latched
on the rising edge of RFC or TCC. TC0 is transmitted first.
INPUT - TTL: 10-Bit Transmit Bus for Channel D. Parallel data on this bus is latched
on the rising edge of RFC, TCC or TCD. TD0 is transmitted first.
INPUT - Differential PECL or TTL: This rising edge of RFC+/- provides the reference
clock, at 1/10^th or 1/20^th of the baud rate (depending on RFCM) to the Clock
Multiplying PLL. If RFC+/- is used, either leave RFCT open or set RFCT HIGH.
Internally biased to V_DD/2. If all TCi inputs are HIGH, the rising edge of RFC will
latch TXi[0:9] on all four channels.
INPUT - TTL: TTL Reference Clock. This rising edge of RFCT provides the
reference clock, at 1/10^th or 1/20^th of the baud rate (depending on RFCM) to the Clock
Multiplying PLL. If RFCT is used, set RFC+ HIGH and leave RFC- open. If all TCi
inputs are HIGH, the rising edge of RFCT will latch TXi[0:9] on all four channels
INPUT - TTL: Reference Clock Mode Select. When LOW, RFC is at 1/20^th of the
transmit baud rate (i.e., 62.5MHz for 1.25Gb/s). When HIGH, RFC is at
1/10^th the baud rate (i.e., 125MHz for 1.25Gb/s).
OUTPUT - TTL: These are identical copies of the transmit baud rate clock divided by
10.
INPUT - TTL: Per Channel Transmit Byte Clock for Channel x. All four channels’
parallel TXi[0:9] inputs may be timed to RFC, TCC, or independently to TCi. Refer to
the Serializer description.
INPUT - TTL: Latch Transmit Byte Clocks. When LOW, internal PLLs align clocks
with each of the transmit byte clocks, if present. Data may be corrupted when LOW.
When HIGH, alignment will remain static regardless of actual TCi location.
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© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: [phone] • Email: [e-mail]
Internet: www.vitesse.com
G52307-0, Rev 2.2
10/10/00