VSC8163 Datasheet, PDF (6/20 Pages) Vitesse Semiconductor Corporation – OC-48 16:1 SONET/SDH MUX with Clock Generator

VITESSE
SEMICONDUCTOR CORPORATION
OC-48 16:1 SONET/SDH
MUX with Clock Generator
Preliminary Data Sheet
VSC8163
input signal swing should be centered about this common-mode reference voltage (V_CMI) and not exceed the
maximum allowable amplitude. For single-ended, DC-coupling operations, it is recommended that the user pro-
vides an external reference voltage. The external reference should have a nominal value equivalent to the com-
mon mode switch point of the DC-coupled signal, and can be connected to either side of the differential gate.
Power Supplies
This device is specified as a LVPECL device with a single positive 3.3V supply. Should the user desire to
use the device in an ECL environment with a negative 3.3V supply, then V_CC will be ground and V_EE will be
-3.3V. If used with V_EE tied to -3.3V, the TTL control signals are still referenced to V_EE.
Decoupling of the power supplies is a critical element in maintaining the proper operation of the part. It is
recommended that the V_CC power supply be decoupled using a 0.1µF and 0.01µF capacitor placed in parallel
on each V_CC power supply pin as close to the package as possible. If room permits, a 0.001µF capacitor should
also be placed in parallel with the 0.1µF and 0.01µF capacitors mentioned above. Recommended capacitors are
low inductance ceramic SMT X7R devices. For the 0.1µF capacitor, a 0603 package should be used. The
0.01µF and 0.001µF capacitors can be either 0603 or 0402 packages.
Extra care needs to be taken when decoupling the analog power supply pins (V_CCANA). In order to maintain
the optimal jitter and loop bandwidth characteristics of the PLL contained in the VSC8163, the analog power
supply pins should be filtered from the main power supply with a 10µH C-L-C pi filter. If preferred, a ferrite
bead may be used to provide the isolation. The 0.1µF and 0.01µF decoupling capacitors are still required and
must be connected to the supply pins between the device and the C-L-C pi filter (or ferrite bead).
For low frequency decoupling, 47µF tantalum low inductance SMT caps are sprinkled over the board’s
main +3.3V power supply and placed close to the C-L-C pi filter.
If the device is being used in an ECL environment with a -3.3V supply, then all references to decoupling
V_CC must be changed to V_EE, and all references to decoupling 3.3V must be changed to -3.3V.
Figure 8: PLL Power Supply Decoupling Scheme
V_CC
10µF
0.1µF
V_EE
10µH
0.1µF
0.01µF
V_{CC_ANA}
V_{EE_ANA}
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© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: [phone] • Email: [e-mail]
Internet: www.vitesse.com
G52216-0, Rev 3.3
01/05/00