VSC9142 Datasheet, PDF (28/30 Pages) Vitesse Semiconductor Corporation – SONET/SDH 2.5Gbps Transport Terminating Transceiver

G56054, Rev 1.0
VSC9142
STS-48c Physical Layer Packet/ATM Over SONET/SDH Device
Table 1.1 Hardware Signal Definitions (10 of 12)
Pin Label Pad
TTOHEN
C14
I/O Type Signal Name
Description
I
TTL Transmit Transport When asserted, this signal enables insertion of TTOH[3..0] in the
Overhead Enable corresponding transport overhead octet of the outgoing STS-48
data stream. Transport overhead for the entire STS-48 is input as
4-bit nibbles on TTOH[3..0] (see TTOH[3..0] description).
TTOHEN assertion during the first nibble of an overhead octet
enables the corresponding overhead octet on TTOH[3..0].
Note: The Section and Line transmit overhead processing blocks
(TSOP/TLOP) can selectively overwrite overhead octets inserted
through the TTOH interface.
TTOH[0]
D16
I
TTL Transmit Transport These are the data inputs for the transmit transport overhead
TTOH[1]
C16
Overhead Data
(Section and Line) octets to be inserted in the outgoing STS-48
TTOH[2]
D15
TTOH[3]
C15
data stream. TTOH[3..0] carries the entire transport overhead in
the order the octets are to be inserted. The most significant
nibble (first received) is input first. TTOH[3] is the most significant
bit. TTOH[3..0] is sampled on the rising edge of TTOHCLK.
D[0]
AB6 _{I/O TTL CPU Data}
This is a bidirectional data bus that provides microcontroller
D[1]
AC4
read/write access for transferring data to and from the device’s
D[2]
AD4
internal registers.
D[3]
AB7
D[4]
AC5
D[5]
AC6
D[6]
AD6
D[7]
AC7
A[0]
AB9
I
TTL _{CPU Address}
This is the register address bus used to select specific internal
A[1]
AD7
registers during microcontroller read/write accesses.
A[2]
AA10
A[3]
AC9
A[4]
AD9
A[5]
AC10
A[6]
AB11
A[7]
AC11
A[8]
AB13
Page 28
1.0 Product Description.