VSC9142 Datasheet, PDF (25/30 Pages) Vitesse Semiconductor Corporation – SONET/SDH 2.5Gbps Transport Terminating Transceiver

G56054-0, Rev 1.0
SONET/SDH 2.5Gbps Transport Terminating Transceiver
VSC9142.
Table 1.1 Hardware Signal Definitions (7 of 12)
Pin Label Pad I/O Type Signal Name
Description
POS Mode: AB2 O TTL Receive End of
REOP
Packet
POS Mode only: REOP is asserted (active high) to indicate that
RDATx contains the last valid octet of the packet.
POS Mode: AA2
RVAL
ATM Mode:
RUEMPTY*/
RUCLAV
O TTL
Receive Data Valid
or
Receive
Empty/Cell
Available
POS Mode: RVAL asserted (active high) indicates that the
recevie data signals (RDATx, RSOP, REOP, RMOD, RPRTY,
and RERR) are valid. When RAL is low, all receive signals are
invalid and must be disregarded. RVAL transitions low when the
Rx FIFO is empty or the end of a packet is reached, and data will
not be removed from the Rx FIFO while RVAL is low. Once
deasserted, RVAL remains so until the current PHY has been
deselected.
ATM Mode: RUEMPTY*/RUCLAV indicates “Empty” or “Cell
Available” status of the UTOPIA receive interface for flow control.
RUEMPTY* is for word-level flow control; RUCLAV is for cell-
level flow control. Polarity is selectable via an internal register bit
(i.e., RUCLAV active high/RUEMPTY* active low, or vice versa).
POS Mode: W4 O TTL Receive Error
RERR
Indicator
POS Mode only: An asserted RERR flag (active high) indicates
that the packet contained an error (i.e., abort/FCS error). The
RERR flag is only asserted during EOP-marked words.
POS Mode: AA3
RENB
ATM Mode:
I TTL Receive Read
Enable
POS Mode: RENB is used by the Packet layer to indicate that
the RVAL, RSOP, RPRTY, RDATx, RMODx, REOP, and RERR
signals will be sampled at the end of the nest cycle (active low).
RUENB*
ATM Mode: RUENB* is used by the ATM layer to indicate that
RUDATA, RUSOC, and RPRTY will be sampled at the end of the
nest cycle (active low).
POS Mode: Y4
RFCLK
ATM Mode:
RUCLK
I TTL Receive FIFO
Write Clock
or
Receive Write
Clock
POS Mode: RFCLK is a reference clock provided by the Packet
layer to the PHY layer to synchronize transfers on RDATx.
ATM Mode: RUCLK is a reference clock provided by the ATM
layer to the PHY layer to synchronize transfers on RUDATAx.
POS Mode: AA4
RFCLKO
ATM Mode:
RUCLKO
O TTL
Receive FIFO
Write Clock
Looped
or
Receive Write
Clock Looped
POS Mode: RFCLKO is the RFCLK transfer synchronization
reference clock looped out.
ATM Mode: RUCLKO is the RUCLK transfer synchronization
reference clock looped out.
TXTS
AA6 O TTL Transmit Time
Stamp
TXTS is an active high pulse generated when a cell/packet exits
the TPP block. The difference in time between a TXTS pulse
and a TSOP/TUSOC pulse can be used to determine transmit
FIFO latency.
RXTS
AC3 O TTL Receive Time
Stamp
RXTS is an active high pulse generated when a new cell/packet
arrives in the RPP block. The difference in time between an
RXTS pulse and an RSOP/RUSOC pulse is used to determine
receive FIFO latency.
LOS
AB5 O TTL Loss of Signal
This is a status signal for loss of signal (LOS) detection (active
high). LOS status is also indicated by an internal register bit.
LOF
AA13 O TTL Loss of Frame
This is a status signal for loss of frame (LOF) detection (active
high). LOF status is also indicated by an internal register bit.
LCD-P
AB4 O TTL Loss of Cell
Delineation
This signal is asserted when the cell delineation state machine is
not in SYNC state. This alarm indication is also available via
internal register access.
4.0 Electrical & Mechanical Data
Page 25.