VSC7140 Datasheet, PDF (2/12 Pages) Vitesse Semiconductor Corporation – 1.0625 Gb/s Fibre Channel Dual Repeater / Hub Node

VITESSE
SEMICONDUCTOR CORPORATION
1.0625 Gb/s Fibre Channel
Dual Repeater / Hub Node
Data Sheet
VSC7140
Functional Description
The VSC7140 contains two fully integrated repeaters to improve signal quality and determine whether the
input to the repeater contains invalid Fibre Channel data. Each repeater consists of a Clock Recovery Unit
(CRU) and a digital Signal Detect Unit (SDU). The CRU locks onto the incoming signal, generates a recovered
clock (nominally 1.0625 GHz) and uses this clock to resynchronize the incoming signal. The recovered data
has improved signal quality due to amplification and jitter attenuation. Recovered data is retimed to the recov-
ered clock, not to the reference clock, REFCLK. The design of the CRU eliminates the need for any Lock-to-
Reference signal since, in the absence of data, the CRU locks onto REFCLK automatically which eliminates the
need for any external control.
The Signal Detect Units (SDUs) test the recovered data from the CRUs for invalid Fibre Channel data by
looking for run length errors (more than 5 consecutive 1’s or 0’s) and the absence of a seven bit pattern found in
the K28.5 character of either disparity (‘0000101’ or ‘1111010’). This K28.5 pattern should occur between all
valid Fibre Channel frames. The maximum length of a Fibre Channel frame is 2148 bytes (or 21,480 encoded
bits) and the SDU divides time into 1-1/2 maximum frames with a 15-bit counter (~31 microseconds). At the
end of each interval, any run length or K28.5 errors which occured during the interval are stored internally for
use by the state machine which drives the SDU output, FAILn-.
The ERRSEL input controls both SDUs while the FAILn- outputs provide the status of each SDU. ERR-
SEL selects two different modes generated by the SDU; Single Frame (LOW) or Multiple Frame (HIGH) error
modes. In Single Frame Error Mode, any error condition that occurs within the 1-1/2 frame interval causes
FAILn- to be asserted LOW immediately after that interval. FAILn- remains asserted until immediately after an
error free interval. In Multiple Frame Error Mode, FAILn- is asserted after four consecutive intervals containing
errors and remains asserted until after four consecutive error-free intervals occur. The intent of the Multiple
Frame Error Mode is to allow FAIL1- or FAIL2- to be directly connected to the Port Bypass Circuit controls,
SEL1 or SEL2, in order to configure the part to isolate RX1 or RX2 whenever invalid data is present. Single
Frame Error Mode allows the user to develop their own algorithm for monitoring data and controlling SEL1 or
SEL2.
A TTL reference clock, REFCLK, is used by the internal Clock Multiplier Unit (CMU) to generate a baud
rate clock (nominally 1.0625 GHz). If REFSEL is HIGH, the CMU multiplies REFCLK (nominally 106.25
MHz) by a factor of 10. If REFSEL is LOW, the CMU multiplies REFCLK (nominally 53.125 MHz) by a fac-
tor of 20. The user must ensure that REFSEL is properly set in order to match the frequency of REFCLK.
Three Port Bypass Circuits (PBC) contain differential 2:1 muxes operating at 1.0625 Gb/s for routing serial
data. SEL1 configures PBC1 to select either the output of CRU1 (HIGH) or SI1 (LOW) to drive SO1. SEL2
configures PBC2 to select either the output of CRU2 (HIGH) or the output of PBC3 (LOW) to drive SO2.
HUB configures PBC3 to select either the output of PBC1 (HIGH) or SI2 (LOW) to drive the input to PBC2.
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© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: [phone] • Email: [e-mail]
Internet: www.vitesse.com
G52180-0, Rev 4.0
10/23/00