SI9142 Datasheet, PDF (9/11 Pages) Vishay Siliconix – Synchronous Buck Controller for High Performance Processors

Si9142
Vishay Siliconix
DESCRIPTION OF OPERATION
The Si9142 is a voltage mode synchronous buck controller
designed to power a high performance microprocessor power
supply. The voltage mode control provides efficiency and cost
saving advantages over current mode control in high output
current converters by eliminating the current sense resistor.
The Si9142 provides ultra-fast (5-µsec) transient response
time and all the necessary protection circuits demanded by
microprocessor supply designers.
Pin 1. NI - Non-Inverting Input
NI is the non-inverting input of the error amplifier. For
converter output voltages equal to or greater than 1.3 V, the
NI pin can be connected directly to V_REF. For converter output
voltages less than 1.3 V, the NI pin can be connected to V_REF
through a voltage divider.
Pin 2. SS/Enable - Soft-Start/Enable
Soft-start is accomplished by connecting a capacitor from this
pin to AGND. The soft-start functions as a constant current
source into this capacitor. A logic low (≤0.8 V) on this pin
disables the output gate drives; the oscillator continues to
function. A logic high (≥2.4 V) enables the output gate drives,
assuming the input voltage is above the UVLO threshold, and
that no over-voltage or over-current condition exists.
Pins 3 and 4. FB and COMP - Error Amplifier
FB is the inverting input of the error amplifier. The voltage on
this pin is also connected internally to the input terminals of
the OVP and PWR_GOOD comparators for fault detection
and protection. The error amplifier has 10-MHz gain-
bandwidth when connected to a 20-pF load with 5-V input
voltage. COMP is the output of the error amplifier. The output
voltage is clamped at a maximum level to avoid long delays
due to saturation during large transient conditions. The
minimum COMP voltage is a diode drop below the 0% duty
cycle voltage; the maximum voltage is a diode drop above the
94% duty cycle voltage.
Pin 5. V_CC - Input Voltage
The V_CC pin should be connected to the input voltage for
optimum performance. The input voltage range of the Si9142
is specified to operate with either +5 VDC or +12 VDC. In
order to accommodate the tolerance of the +12 V, and the
possibility of using this controller in 2-cell Li+ notebook
applications with a battery charger, the input voltage is rated
up to +15-V absolute maximum.
Pin 6. V_REF - Reference Voltage
The reference voltage is designed to produce 1.30 V ±1.6%
over the line and temperature range, to produce equally tight
output regulation of the converter. The reference should be
decoupled with at least 100-nF capacitance. The reference is
capable of driving 1mA of external load.
Pin 7. AGND - Analog Ground
AGND is the analog ground for the low power circuitry in the
converter. This ground should be separated locally from
PGND, and should have a separate run back to the input
bypass capacitors.
Pin 8. R_OSC - Oscillator Timing Resistor
A resistor from this pin to AGND determines the internal
switching frequency of the oscillator. The internal circuitry
produces 10% frequency accuracy with a 1% timing resistor.
The oscillator is capable of switching at up to 1 MHz.
Pin 10. SYNC - Synchronization
The SYNC signal is generated from the internal oscillator.
When the oscillator is ramping positive, SYNC will be logic
high; when the oscillator is ramping negative, SYNC will be
logic low. The SYNC pin can be used to synchronize the
Si9142 to an external clock. In particular, if several Si9142s
have their SYNC pins shorted together, they will all switch at
the same frequency and in phase, with the frequency being
set by the fastest oscillator.
Pin 11. PWR_GOOD - Open Collector Power Good Signal
This pin signals the status of the output voltage. The window
comparator is set at ±12% of the voltage at the NI pin, with a
tolerance of 5%. The PWR_GOOD signal is an open drain
output capable of sinking 2 mA.
Pins 12 and 13. PGND - Power Ground
PGND is the power ground for the high power circuitry in the
converter. This ground should be separated locally from
AGND, and should have a separate plane run back to the
input bypass capacitors.
Pins 14 and 18. D_L and D_H - Low- and High-Side Gate
Drives
D_H is the high-side and D_L the low-side gate drive to the
external MOSFETs. Both can source and sink 2.5-A peak with
4.5-V gate drives. The timing sequence of high- and low-side
gate drives is shown in Figure 1. The internal break-before-
make time interval (t_BBM) of 55 nsec prevents shootthrough
current in the external MOSFETs. The ringing from the gate
drive output’s trace inductance can produce negative voltages
on D_H and D_L as much as 2-V negative with respect to PGND.
The gate drive circuit is capable of withstanding these
negative voltages without any functional defects.
Pins 15 and 16. V_L(out) and V_L(in) - +5.5-V Linear Regulator
V_L(out) produces a +5.5-V output used as the gate drive
voltage for both the high- and low-side external MOSFETs.
The gate drive voltage for the high-side MOSFET is
bootstrapped (V_L(out) - V_DIODE) above the input voltage.
V_L(out) should be bypassed with at least 4.7 µF of decoupling
FaxBack 408-970-5600, request 70750
www.siliconix.com
S-60752—Rev. C, 05-Apr-99
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