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DG2501 Datasheet, PDF (8/9 Pages) Vishay Siliconix – Low Leakage, Low Parasitic and Low Charge Injection, Quad SPST Analog Switches
www.vishay.com
DG2501, DG2502, DG2503
Vishay Siliconix
TEST CIRCUIT
V+
Switch
Input
Logic
Input
V+
S
D
IN
GND
Switch Output
VOUT
RL
300 Ω
CL
35 pF
Logic
Input
VINH
VINL
50 %
Switch
Output
0V
tON
tr < 5 ns
tf < 5 ns
0.9 x VOUT
tOFF
CL (includes fixture and stray capacitance)
VOUT = VD
RL
RL + RON
Fig. 3 - Switching Time
Logic "1" = Switch On
Logic input waveforms inverted for switches that have
the opposite logic sense.
V+
Vgen
Rgen
+
VIN = 0 - V+
V+
D
S
IN
GND
VOUT
VOUT
V OUT
CL = 1 nF
IN
On
Off
On
Q = V OUT x CL
IN depends on switch configuration: input polarity
determined by sense of switch.
Fig. 4 - Charge Injection
V+
10 nF
V+
S
D
IN 0 V, 2.4 V
RL
Analyzer
GND
VD
Off Isolation = 20 log VS
Fig. 5 - Off-Isolation
V+
10 nF
V+
D
IN
0 V, 2.4 V
S
GND
Meter
HP4192A
Impedance
Analyzer
or Equivalent
f = 1 MHz
Fig. 6 - Channel Off/On Capacitance
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?62962.
S14-1059-Rev. A, 19-May-14
8
Document Number: 62962
For technical questions, contact: analogswitchtechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000