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DG201BMIL Datasheet, PDF (8/12 Pages) Vishay Siliconix – Improved Quad CMOS Analog Switches
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www.vishay.com
APPLICATIONS
DG201BMIL, DG202BMIL
Vishay Siliconix
+ 15 V
V+
Logic Input
Low = Sample
High = Hold
+ 15 V
- 15 V
-
LM101A
VIN
+
5M
5.1 M
30 pF
Aquisition Time
Aperature Time
Sample to Hold Offset
Droop Rate
= 25 µs
= 1 µs
= 5 mV
= 5 mV/s
V-
- 15 V
DG201B
1k
50 pF
Fig. 6 - Sample-and-Hold
+ 15 V
J202
200
1000 pF
2N4400
J500
J507
- 15 V
VOUT
fC4
Select
TTL
Control
fC3
Select
fC2
Select
fC1
Select
C4
150 pF
C3
1500 pF
C2
0.015 µF
C1
0.15 µF
+ 15 V
V1
V- DG201B GND
R1 = 10 k
R2 = 10 k
- 15 V
R3 = 1 M
+ 15 V
-
LM101A
- 15 V
+
30 pF
160
120
80
fC1
40
fC2 fC3 fC4
0
fL1
fL2
fL3
fL4
- 40
1
10
100 1K
10K 100K 1M
f - Frequency (Hz)
VOUT
AL (Voltage Gain Below Break Frequency) =
1
fC (Break Frequency) = 2 R3CX
fL (Unity Gain Frequency) =
1
2 R1CX
Max. Attenuation =
RDS(on) ≈ - 47 dB
10 k
R3
R1 = 100 (40 dB)
Fig. 7 - Active Low Pass Filter with Digitally Selected Break Frequency
S12-0631-Rev. A, 19-Mar-12
8
Document Number: 63374
For technical questions, contact: AnalogSwitchtechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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