SI9161 Datasheet, PDF (6/12 Pages) Vishay Siliconix – Optimized-Efficiency Controller for RF Power Amplifier Boost Converter

Si9161
Vishay Siliconix
PIN CONFIGURATIONS
PIN DESCRIPTION
Pin 1: V_DD
The positive power supply for all functional blocks except
output driver. A bypass capacitor of 0.1 µF (minimum) is
recommended.
Pin 2: LL
A logic high on this pin allows normal operation. A logic low
places the chip in light-load optimized-efficiency mode. In
light-load mode, the oscillator frequency is reduced and D_R
goes high, disabling synchronous rectification. Do not leave
pin unconnected.
Pin 3: D_MAX
Used to set the maximum duty cycle.
Pin 4: COMP
This pin is the output of the error amplifier. A compensation
network is connected from this pin to the FB pin to stabilize
the system. This pin drives one input of the internal pulse
width modulation comparator.
Pin 5: FB
The inverting input of the error amplifier. An external resistor
divider is connected to this pin to set the regulated output
voltage. The compensation network is also connected to this
pin.
Pin 6: NI
The non-inverting input of the error amplifier. In normal
operation it is externally connected to V_REF or an external
reference.
Pin 7: V_REF
This pin supplies a 1.5-V reference.
Pin 8: GND (Ground)
Pin 9: ENABLE
A logic high on this pin allows normal operation. A logic low
places the chip in the standby mode. In standby mode, normal
operation is disabled, supply current is reduced, the oscillator
stops, and D_S goes low while D_R goes high.
Pin 10: R_OSC
A resistor connected from this pin to ground sets the
oscillator’s capacitor (C_OSC) charge and discharge current.
See the oscillator section of the description of operation.
Pin 11: C_OSC
An external capacitor is connected to this pin to set the
normal oscillator frequency.
f_OSC
≅
-------------⁰---^.--⁷---⁰--------------
R_OSC × C_OSC
(at V_DD = 5.0 V)
Pin 12: UVLO_SET
This pin will place the chip in the standby mode if the
UVLO_SET voltage drops below 1.2 V. Once the UVLO_SET
voltage exceeds 1.2 V, the chip operates normally. There is a
built-in hysteresis of 200 mV.
Pin 13: P_GND
The negative return for the V_S supply.
Pin 14: D_S
This CMOS push-pull output pin drives the external n-channel
MOSFET. This pin will be low in the standby mode. A break-
before-make function between D_S and D_R is built-in.
S-60752—Rev. B, 05-Apr-99
6
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