SI9102 Datasheet, PDF (6/7 Pages) Vishay Siliconix – 3-W High-Voltage Switchmode Regulator

Si9102
Vishay Siliconix
Note: During start-up or when V_CC drops below 9.4-V the
start-up circuit is capable of sourcing up to 20 mA. This may
lead to a high level of power dissipation in the IC (for a 48-V
input, approximately 1 W). Excessive start-up time caused by
external loading of the V_CC supply can result in device
damage. Figure 4 gives the typical pre-regulator current at
start-up as a function of input voltage.
BIAS
To properly set the bias for the Si9102, a 390-kW resistor
should be tied from BIAS to −V_IN. This determines the
magnitude of bias current in all of the analog sections and the
pull-up current for the SHUTDOWN and RESET pins. The
current flowing in the bias resistor is nominally 15 mA.
Reference Section
The reference section of the Si9102 consists of a temperature
compensated buried zener and trimmable divider network.
The output of the reference section is connected internally to
the non-inverting input of the error amplifier. Nominal reference
output voltage is 4 V. The trimming procedure that is used on
the Si9102 brings the output of the error amplifier (which is
configured for unity gain during trimming) to within "1% of 4 V.
This automatically compensates for the input offset voltage in
the error amplifier.
The output impedance of the reference section has been
purposely made high so that a low impedance external voltage
source can be used to override the internal voltage source, if
desired, without otherwise altering the performance of the
device.
Error Amplifier
Closed-loop regulation is provided by the error amplifier, which
is intended for use with “around-the-amplifier” compensation.
A MOS differential input stage provides for low input current.
The noninverting input to the error amplifier (V_REF) is internally
connected to the output of the reference supply and should be
bypassed with a small capacitor to ground.
Oscillator Section
The oscillator consists of a ring of CMOS inverters, capacitors,
and a capacitor discharge switch. Frequency is set by an
external resistor between the OSC in and OSC out pins. (See
Figure 5 for details of resistor value vs. frequency.) The
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DISCHARGE pin should be tied to −V_IN for normal internal
oscillator operation. A frequency divider in the logic section
limits switch duty cycle to v 50% by locking the switching
frequency to one half of the oscillator frequency.
Remote synchronization can be accomplished by capacitive
coupling of a synchronization pulse into the OSC IN terminal.
For a 5-V pulse amplitude and 0.5-ms pulse width, typical
values would be 100 pF in series with 3 kW to OSC IN.
SHUTDOWN and RESET
SHUTDOWN and RESET are intended for overriding the
output MOSFET switch via external control logic. The two
inputs are fed through a latch preceding the output switch.
Depending on the logic state of RESET, SHUTDOWN can be
either a latched or unlatched input. The output is off whenever
SHUTDOWN is low. By simultaneously having SHUTDOWN
and RESET low, the latch is set and SHUTDOWN has no effect
until RESET goes high. The truth table for these inputs is given
in Table 1.
Both pins have internal current source pull-ups and should be
left disconnected when not in use. An added feature of the
current sources is the ability to connect a capacitor and an
open-collector driver to the SHUTDOWN or RESET pins to
provide variable shutdown time.
Table 1. Truth Table for the SHUTDOWN and RESET
Pins
SHUTDOWN
H
H
L
L
RESET
H
H
L
L
Output
Normal Operation
Normal Operation (No Change)
Off (Not Latched)
Off (Latched)
Off (Latched, No Change)
Output Switch
The output switch is a 7-W , 200-V lateral DMOS device. Like
discrete MOSFETs, the switch contains an intrinsic body-drain
diode. However, the body contact in the Si9102 is connected
internally to −V_IN and is independent of the SOURCE.
Document Number: 70001
S-42040—Rev. G, 15-Nov-04