DG444_11 Datasheet, PDF (6/12 Pages) Vishay Siliconix – Quad SPST CMOS Analog Switches

DG444, DG445
Vishay Siliconix
SCHEMATIC DIAGRAM Typical Channel
V+
V_L
V_IN
GND
V-
TEST CIRCUITS
Level
Shift/
Drive
Figure 1.
S
V-
V+
D
± 10 V
3V
+5V
+ 15 V
V_L
S
IN
GND
V+
D
R_L
1 k
V-
- 15 V
V_O
C_L
35 pF
Logic
Input
Switch
Input
3V
50 % 50 %
t_r < 20 ns
t_f < 20 ns
0V
t_OFF
V_S
V_O
80 %
80 %
Switch
0V
Output
t_ON
C_L (includes fixture and stray capacitance)
Figure 2. Switching Time
Note:
Logic input waveform is inverted for DG445.
+5V
+ 15 V
V_L
R_g
S
V+
D
V_g
3V
IN
GND
V-
V_O
C_L
1 nF
V _O
V_O
IN_X
OFF
ON
OFF
(DG444)
- 15 V
OFF
IN_X
(DG445)
Figure 3. Charge Injection
ON
Q = V_O x C_L
OFF
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Document Number: 70054
6
S11-0984-Rev. G, 23-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000