DG444 Datasheet, PDF (6/9 Pages) Intersil Corporation – Monolithic, Quad SPST, CMOS Analog Switches

DG444/445
Vishay Siliconix
SCHEMATIC DIAGRAM (TYPICAL CHANNEL)
V+
V_L
V_IN
GND
V–
Level
Shift/
Drive
S
V–
V+
D
FIGURE 1.
TEST CIRCUITS
"10 V
3V
+5 V
+15 V
V_L
S
IN
GND
V+
D
R_L
1 kW
V–
V_O
C_L
35 pF
–15 V
C_L (includes fixture and stray capacitance)
Logic
Input
Switch
Input
3V
50% 50%
0V
t_r <20 ns
t_f <20 ns
t_OFF
V_S
V_O
80%
80%
Switch
0V
Output
t_ON
Note:
Logic input waveform is inverted for DG445.
FIGURE 2. Switching Time
+5 V
+15 V
V_L
R_g
S
V+
D
V_g
3V
IN
GND
V–
V_O
C_L
1 nF
V_O
IN_X
OFF
ON
(DG444)
DV_O
OFF
–15 V
OFF
IN_X
(DG445)
FIGURE 3. Charge Injection
ON
Q = DV_O x C_L
OFF
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4-6
Document Number: 70054
S-52433—Rev. F, 06-Sep-99