DG401B Datasheet, PDF (6/10 Pages) Vishay Siliconix – Low-Power, High-Speed CMOS Analog Switches

DG401B/403B/405B
Vishay Siliconix
New Product
SCHEMATIC DIAGRAM (TYPICAL CHANNEL)
V+
V_IN
GND
V−
Level
Shift/
Drive
FIGURE 1.
S
V−
V+
D
TEST CIRCUITS
V_O is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing edge of the output waveform.
"10 V
+15 V
V+
S
D
3V
Logic
Input
0V
50%
t_r <20 ns
t_f <20 ns
V_O
Switch
Input*
V_S
90%
t_OFF
V_O
IN
GND
V−
−15 V
R_L
1 kW
C_L
35 pF
Switch
0V
Output
t_ON
Switch
Input*
−V_S
V_O
90%
C_L (includes fixture and stray capacitance)
V_O = V_S
R_L
R_L + r_DS(on)
*V_S = 10 V for t_ON, V_S = −10 V for t_OFF
Note: Logic input waveform is inverted for switches that
have the opposite logic sense control
FIGURE 2. Switching Time
+15 V
V_S1
S₁
V_S2
S₂
IN
GND
V+
D₁
D₂
V−
V_O2
V_O1
R_L2
C_L2
R_L1
C_L1
−15 V
C_L (includes fixture and stray capacitance)
Logic
3V
Input
0V
V_S1
V_O1
Switch
0V
Output
V_S2
V_O2
Switch
0V
Output
FIGURE 3. Break-Before-Make
50%
90%
90%
t_D
t_D
www.vishay.com
6
Document Number: 73069
S-42444—Rev. A, 10-Jan-05