DG528_11 Datasheet, PDF(5/12 Page) Vishay Siliconix – Latchable Single 8-Ch/Differential 4-Ch Analog Multiplexers

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DG528_11 Datasheet, PDF (5/12 Pages) Vishay Siliconix – Latchable Single 8-Ch/Differential 4-Ch Analog Multiplexers

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SCHEMATIC DIAGRAM (TYPICAL CHANNEL)

DG528, DG529

Vishay Siliconix

V+

GND

V-

VREF

V+

V-

V+

V-

V+

V-

DO QO

V-

V+

Dn Qn

V-

V+

Latches

Level

Shift

Decode

V-

V+

CLK

RESET

V-

V+

Figure 1.

DETAILED DESCRIPTION

The internal structure of the DG528/DG529 includes a 5-V

logic interface with input protection circuitry followed by a

latch, level shifter, decoder and finally the switch constructed

with parallel n- and p-channel MOSFETs (see Figure 1).

The logic interface circuit compares the TTL input signal

against a TTL threshold reference voltage. The output of the

comparator feeds the data input of a D type latch. The level

sensitive D latch continuously places the DX input signal on

the QX output when the WR input is low, resulting in transpar-

ent latch operation. As soon as WR returns high, the latches

hold the data last present on the DX input, subject to the mini-

mum input timing requirements.

Following the latches the QX signals are level shifted and

decoded to provide proper drive levels for the CMOS

switches. This level shifting insures full on/off switch operation

for any analog signal present between the V+ and V- supply

rails.

The EN pin is used to enable the address latches during the

WR pulse. It can be hard-wired to the logic supply or to V+ if

one of the channels will always be used (except during a reset)

or it can be tied to address decoding circuitry for memory

mapped operation. The RS pin is used as a master reset. All

latches are cleared regardless of the state of any other latch

or control line. The WR pin is used to transfer the state of the

address control lines to their latches, except during a reset or

when EN is low (see Truth Tables).

A0, A1, (A2)

50 %

80 %

Figure 2.

80 %

Switch VO

Output

50 %

tRS

tOFF (RS)

Figure 3.

80 %

Document Number: 70068

www.vishay.com

S11-1029âRev. D, 23-May-11

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

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